An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Data movement between the processing units and the memory in traditional von Neumann architecture is creating the “memory wall” problem. To bridge the gap, two approaches, the memory-rich processor (more on-chip memory) and the compute-capable memory (processing-in-memory) have been studied. However, the first one has strong computing capability but limited memory capacity/bandwidth, whereas the second one is the exact the opposite.To address the challenge, we propose DRISA, a DRAM-based Reconfigurable In-Situ Accelerator architecture, to provide both powerful computing capability and large memory capacity/bandwidth. DRISA is primarily composed of DRAM memory arrays, in which every memory bitline can perform bitwise Boolean logic operations (such as NOR). DRISA can be reconfigured to compute various functions with the combination of the functionally complete Boolean logic operations and the proposed hierarchical internal data movement designs. We further optimize DRISA to achieve high performance by simultaneously activating multiple rows and subarrays to provide massive parallelism, unblocking the internal data movement bottlenecks, and optimizing activation latency and energy. We explore four design options and present a comprehensive case study to demonstrate significant acceleration of convolutional neural networks. The experimental results show that DRISA can achieve 8.8× speedup and 1.2× better energy efficiency compared with ASICs, and 7.7× speedup and 15× better energy efficiency over GPUs with integer operations.CCS CONCEPTS• Hardware → Dynamic memory; • Computer systems organization → reconfigurable computing; Neural networks;

DRISA: a DRAM-based Reconfigurable In-Situ Accelerator

In one embodiment, a conductive interconnect ( 38 ) is formed in a semiconductor device by depositing a dielectric layer ( 28 ) on a semiconductor substrate ( 10 ). The dielectric layer ( 28 ) is then patterned to form an interconnect opening ( 29 ). A tantalum nitride barrier layer ( 30 ) is then formed within the interconnect opening ( 29 ). A catalytic layer ( 31 ) comprising a palladium-tin colloid is then formed overlying the tantalum nitride barrier layer ( 30 ). A layer of electroless copper ( 32 ) is then deposited on the catalytic layer ( 31 ). A layer of electroplated copper ( 34 ) is then formed on the electroless copper layer ( 32 ), and the electroless copper layer ( 32 ) serves as a seed layer for the electroplated copper layer ( 34 ). Portions of the electroplated copper layer ( 34 ) are then removed to form a copper interconnect ( 38 ) within the interconnect opening ( 29 ).

Interconnect structure in a semiconductor device and method of formation

A microelectronic substrate including at least one microelectronic device disposed within an opening in a microelectronic substrate core, wherein an encapsulation material is disposed within portions of the opening not occupied by the microelectronic devices, or a plurality microelectronic devices encapsulated without the microelectronic substrate core. At least one conductive via extended through the substrate, which allows electrical communication between opposing sides of the substrate. Interconnection layers of dielectric materials and conductive traces are then fabricated on the microelectronic device, the encapsulation material, and the microelectronic substrate core (if present) to form the microelectronic substrate.

Microelectronic substrates with integrated devices

A wired circuit board has a metal supporting board, an insulating layer formed on the metal supporting board, a conductive pattern formed on the insulating layer and having a pair of wires arranged in spaced-apart relation, and a semiconductive layer formed on the insulating layer and electrically connected to the metal supporting board and the conductive pattern The conductive pattern has a first region in which a distance between the pair of wires is small and a second region in which the distance between the pair of wires is larger than that in the first region The semiconductive layer is provided in the second region

Wired circuit board

An electronic structure, and associated method of formation, in which a plated metallic layer such as a copper layer, of a plated through hole (PTH) is adhesively coupled to holefill material distributed within the PTH. The holefill material includes a resin such as an epoxy and optionally includes a particulate component such as a copper powder. The adhesive coupling is accomplished by forming an adhesion promoter film on the plated metallic layer such that the adhesion promoter film is bonded to the resin. The adhesion promoter film may include a metallic oxide layer such as layer containing cupric oxide and cuprous oxide, which could be formed from bathing the PTH in a solution of sodium chlorite. Application of a reducing solution of dimethylamine borane to the cuprous oxide layer would convert some of the cuprous oxide to cupric oxide in the metallic oxide layer. Another possibility for an adhesion promoter film is an organometallic layer such as a layer that includes a chemical complex of metal and an organic corrosion inhibitor. Useful organic corrosion inhibitors for this purpose include triazoles, tetrazoles, and imidazoles. The organometallic layer could be formed from bathing the PTH in a bath of hydrogen peroxide, sulfuric acid, and an organic corrosion inhibitor.

Protection of a plated through hole from chemical attack

A 1.1 Mb embedded DRAM macro (eDRAM), for next-generation IBM SOI processors, employs 14 nm FinFET logic technology with $\hbox{0.0174}~\mu\hbox{m}^{2}$ deep-trench capacitor cell. A Gated-feedback sense amplifier enables a high voltage gain of a power-gated inverter at mid-level input voltage, while supporting 66 cells per local bit-line. A dynamic-and-gate-thin-oxide word-line driver that tracks standard logic process variation improves the eDRAM array performance with reduced area. The 1.1 $~$ Mb macro composed of 8 $\times$ 2 72 Kb subarrays is organized with a center interface block architecture, allowing 1 ns access latency and 1 ns bank interleaving operation using two banks, each having 2 ns random access cycle. 5 GHz operation has been demonstrated in a system prototype, which includes 6 instances of 1.1 Mb eDRAM macros, integrated with an array-built-in-self-test engine, phase-locked loop (PLL), and word-line high and word-line low voltage generators. The advantage of the 14 nm FinFET array over the 22 nm array was confirmed using direct tester control of the 1.1 Mb eDRAM macros integrated in 16 Mb inline monitor.

A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access

Ball Grid Array packages having decreased adhesion of the BGA pad to the laminate surface and methods for producing same are provided.

Method and structure for an organic package with improved BGA life

A method for producing small pitch z-axis electrical interconnections in layers of dielectric materials which are applied to printed wiring boards and diverse electronic packages. A method for parallel fabrication of intermediate structures which are subsequently jointed to form a final structure. In addition there is provided a z-interconnected electrical structure, employing dielectric materials such as resin coated copper, employable in the manufacture of diverse type of electronic packages, including printed wiring boards (PWBs), substrates, multi-chip modules and the like.

Method and structure for small pitch z-axis electrical interconnections

A structure of and method for producing a multilayer printed or wiring circuit board, and more particularly a method producing so-called z-axis or multilayer electrical interconnections in a hierarchial wiring structure in order to be able to provide for an increase in the number of inputs and outputs (I/O) in comparison with a standard printed wiring board (PWB) arrangement, and a printed wiring board produced by the method.

Thomas R. Miller

Papers

Protection of a plated through hole from chemical attack

A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access

Method and structure for an organic package with improved BGA life

Method and structure for small pitch z-axis electrical interconnections

Printed wiring board structure with z-axis interconnections