Many metal–insulator–metal systems show electrically induced resistive switching effects and have therefore been proposed as the basis for future non-volatile memories. They combine the advantages of Flash and DRAM (dynamic random access memories) while avoiding their drawbacks, and they might be highly scalable. Here we propose a coarse-grained classification into primarily thermal, electrical or ion-migration-induced switching mechanisms. The ion-migration effects are coupled to redox processes which cause the change in resistance. They are subdivided into cation-migration cells, based on the electrochemical growth and dissolution of metallic filaments, and anion-migration cells, typically realized with transition metal oxides as the insulator, in which electronically conducting paths of sub-oxides are formed and removed by local redox processes. From this insight, we take a brief look into molecular switching systems. Finally, we discuss chip architecture and scaling issues.

http://chialvo.org/Curso/UBACurso/DIA7/Papers/Aono_NatMat_07_Ionic%20Switching%20Memory.pdf

Nanoionics-based resistive switching memories

Redox‐Based Resistive Switching Memories – Nanoionic Mechanisms, Prospects, and Challenges

Bose-Einstein condensation (BEC) has been observed in a dilute gas of sodium atoms. A Bose-Einstein condensate consists of a macroscopic population of the ground state of the system, and is a coherent state of matter. In an ideal gas, this phase transition is purely quantum-statistical. The study of BEC in weakly interacting systems which can be controlled and observed with precision holds the promise of revealing new macroscopic quantum phenomena that can be understood from first principles.

Bose-Einstein condensation in a gas of sodium atoms

Memristive devices are electrical resistance switches that can retain a state of internal resistance based on the history of applied voltage and current. These devices can store and process information, and offer several key performance characteristics that exceed conventional integrated circuit technology. An important class of memristive devices are two-terminal resistance switches based on ionic motion, which are built from a simple conductor/insulator/conductor thin-film stack. These devices were originally conceived in the late 1960s and recent progress has led to fast, low-energy, high-endurance devices that can be scaled down to less than 10 nm and stacked in three dimensions. However, the underlying device mechanisms remain unclear, which is a significant barrier to their widespread application. Here, we review recent progress in the development and understanding of memristive devices. We also examine the performance requirements for computing with memristive devices and detail how the outstanding challenges could be met.

Memristive devices for computing

Despite much progress in semiconductor integrated circuit technology, the extreme complexity of the human cerebral cortex, with its approximately 10(14) synapses, makes the hardware implementation of neuromorphic networks with a comparable number of devices exceptionally challenging. To provide comparable complexity while operating much faster and with manageable power dissipation, networks based on circuits combining complementary metal-oxide-semiconductors (CMOSs) and adjustable two-terminal resistive devices (memristors) have been developed. In such circuits, the usual CMOS stack is augmented with one or several crossbar layers, with memristors at each crosspoint. There have recently been notable improvements in the fabrication of such memristive crossbars and their integration with CMOS circuits, including first demonstrations of their vertical integration. Separately, discrete memristors have been used as artificial synapses in neuromorphic networks. Very recently, such experiments have been extended to crossbar arrays of phase-change memristive devices. The adjustment of such devices, however, requires an additional transistor at each crosspoint, and hence these devices are much harder to scale than metal-oxide memristors, whose nonlinear current-voltage curves enable transistor-free operation. Here we report the experimental implementation of transistor-free metal-oxide memristor crossbars, with device variability sufficiently low to allow operation of integrated neural networks, in a simple network: a single-layer perceptron (an algorithm for linear classification). The network can be taught in situ using a coarse-grain variety of the delta rule algorithm to perform the perfect classification of 3 × 3-pixel black/white images into three classes (representing letters). This demonstration is an important step towards much larger and more complex memristive neuromorphic networks.

Training and operation of an integrated neuromorphic network based on metal-oxide memristors

We developed an atomic switch consisting of an ionic and electronic mixed conductor electrode and a counter metal electrode, having a space of about 1 nm between them. Formation and annihilation of a conductive atomic bridge is controlled using a solid electrochemical reaction, which is caused by applying a certain bias voltage between the electrodes. In this study, we measured the switching time of atomic switches made of silver sulfide and copper sulfide. The switching times were different, and this difference can be attributed to the different activation energies and chemical potentials of the materials.

http://iopscience.iop.org/article/10.1088/1742-6596/61/1/229/pdf

Material dependence of switching speed of atomic switches made from silver sulfide and from copper sulfide

With multi-phase clocking, it is possible to attain a higher operating speed than the internal clock frequency determined by the device performance limitation. When multi-phase clocking is to be applied to larger die sizes or to multi-channel communications, however, it is extremely difficult to distribute the multi phase clock signals to distant local areas without generating inter-phase skew. To achieve a small area for clock distribution, the multi-phase clock generator reported here uses the delay compensation technique. Because this generator does not require a feedback loop, it is compact, adding only a small amount to chip area. Further, it produces accurate phase differences between multi-phase clock signals. Multi-clock generators of this type are applied to 2.5 GHz 4-phase clock distribution of an 8-channel receiver, fabricated with 0.13 /spl mu/m CMOS technology, and operating at 5 Gb/s.

2.5 GHz 4-phase clock generator with scalable and no feedback loop architecture

In the CMOS cross-point LSI described, fully synchronous switching capability for fixed-length ATM cells (packets), as well as the functions of conventional cross-point switches, has been realized. Packet broadcast capability has also been achieved as the result of input-oriented bit-map routing architecture. In order to exchange 32 packet links at the broadband line speed, tristate buffers and control latches with reduced parasitic capacitors have been utilized. The 40 k transistor chip is fabricated with a 1.0- mu m double-metal-layer n-well CMOS technology. The switch matrix is 2.4*3.2 mm. The chip size, 7.4*7.4 mm, is set by the 113 signal pads and the 39 voltage supply pads. Voltage supply nodes for output buffers are completely separated from the others. 250-Mb/s operation has been verified under nominal conditions with a 176-pin PGA package. Operating from a -4.5-V supply at 160 Mb/s, the chip dissipates 1.2 W. >

A 250 Mb/s 32*32 CMOS crosspoint LSI for ATM switching systems

A switch comprising a transistor for selecting a storage cell and a solid electrolyte. In a storage cell, a metal is formed over a drain diffusion layer of a field-effect transistor fabricated on the surface of a semiconductor substrate. A solid electrolyte the carriers of which are the metal is formed on the metal. The solid electrolyte is in contact with the metal with a space therebetween, and the metal is connected to a common ground line. The source of the field-effect transistor is connected to a column address line, and the gate of the transistor is connected to the row address line.

Electric device comprising solid electrolyte

Disclosed is a switching device which is operated by utilizing an electrochemical reaction and comprises an ion conductive layer (54) which is capable of conducting metal ions, a first electrode (49) formed in contact with the ion conductive layer, and a second electrode (58) for supplying metal ions to the ion conductive layer. The switching device is characterized in that an oxygen absorption layer (55) containing a material which is more easily oxidized than the second electrode is formed in contact with the second electrode.

Toshitsugu Sakamoto

Papers

Material dependence of switching speed of atomic switches made from silver sulfide and from copper sulfide

2.5 GHz 4-phase clock generator with scalable and no feedback loop architecture

A 250 Mb/s 32*32 CMOS crosspoint LSI for ATM switching systems

Electric device comprising solid electrolyte

Switching device and method for manufacturing switching device