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Toshitsugu Sakamoto

Researcher at NEC

Publications -  224
Citations -  3567

Toshitsugu Sakamoto is an academic researcher from NEC. The author has contributed to research in topics: Electrode & Crossbar switch. The author has an hindex of 29, co-authored 221 publications receiving 3435 citations. Previous affiliations of Toshitsugu Sakamoto include Korea University.

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Patent

Variable resistance element, semiconductor device including same, and method for manufacturing the element and the device

TL;DR: In this paper, a variable resistance element with an ion conduction layer between the first electrode and the second electrode is described, which can operate at a low voltage, while maintaining a low leak current.
Proceedings ArticleDOI

Robust Cu atom switch with over-400°C thermally tolerant polymer-solid electrolyte (TT-PSE) for nonvolatile programmable logic

TL;DR: In this article, a fully 400°C-processed, standard Cu-BEOL compatible, robust Cu atom switch has been developed featuring an over-400°C high thermally tolerant polymer solid electrolyte (TT-PSE).
Patent

Separation apparatus and process for fabricating separation apparatus

TL;DR: A separator has a specimen separating area comprising a number of recesses defined in an inner wall of a flow passage through which a specimen passes for separating nucleic acid and protein this article.
Journal ArticleDOI

Set/Reset Switching Model of Cu Atom Switch Based on Electrolysis

TL;DR: In this paper, a set/reset switching model of the Cu atom switch based on electrolysis is proposed, where the voltage depends on the resistance of the solid electrolyte, and the modified Faraday's law of electrolysis with exponential factors on current and time well falls on the experimental on-resistance.
Proceedings ArticleDOI

A 2× logic density Programmable Logic array using atom switch fully implemented with logic transistors at 40nm-node and beyond

TL;DR: Xbar of atom switches with 50% and 100% populations mixed and programming lines shared architecture achieves a 2× higher logic density comparing to a commercial PL chip on same technology node of 40 nm.