T
Toshitsugu Sakamoto
Researcher at NEC
Publications - 224
Citations - 3567
Toshitsugu Sakamoto is an academic researcher from NEC. The author has contributed to research in topics: Electrode & Crossbar switch. The author has an hindex of 29, co-authored 221 publications receiving 3435 citations. Previous affiliations of Toshitsugu Sakamoto include Korea University.
Papers
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Journal ArticleDOI
Single-electron transistors fabricated from a doped-Si film in a silicon-on-insulator substrate
TL;DR: In this paper, a doped-thin-Si-film single-electron transistors (DS-SETs) are proposed, which are fabricated from a highly doped Si film in a silicon-on-insulator substate by electron-beam lithography with a high-resolution resist (calixarene) and dry etching with CF4 gas.
Journal ArticleDOI
Solid-electrolyte nanometer switch
Naoki Banno,Toshitsugu Sakamoto,Noriyuki Iguchi,Hisao Kawaura,Shunichi Kaeriyama,Masayuki Mizuno,Kozuya Terabe,Tsuyoshi Hasegawa,Masakazu Aono +8 more
TL;DR: This work develops a solid-electrolyte nonvolatile switch with a low ON resistance and its small size and demonstrates how the Nanobridge enhances the switching voltage and reduces the programming current.
Proceedings ArticleDOI
Highly scalable nonvolatile TiOx/TaSiOy solid-electrolyte crossbar switch integrated in local interconnect for low power reconfigurable logic
Munehiro Tada,Toshitsugu Sakamoto,Yukihide Tsuji,Naoki Banno,Yukishige Saito,Yuko Yabe,S. Ishida,M. Terai,Setsu Kotsuji,Noriyuki Iguchi,Masakazu Aono,Hiromitsu Hada,Naoki Kasai +12 more
TL;DR: In this article, a fully logic compatible, nonvolatile crossbar switch using a dual-layer TiOx/TaSiOy solid-electrolyte, called nano-bridge, has been developed for the first time, which is scalable to 50 nm and beyond.
Journal ArticleDOI
Characteristics and Modeling of Sub-10-nm Planar Bulk CMOS Devices Fabricated by Lateral Source/Drain Junction Control
H. Wakabayashi,T. Ezaki,Toshitsugu Sakamoto,H. Kawaura,Nobuyuki Ikarashi,N. Ikezawa,M. Narihiro,Yukinori Ochiai,T. Ikezawa,Kiyoshi Takeuchi,Toyoji Yamamoto,Masami Hane,Tohru Mogami +12 more
TL;DR: In this paper, a lateral source/drain (S/D) junction control was demonstrated for sub-10-nm planar bulk MOSFETs and the tunneling currents increased with the increase in the temperatures and gate voltages, resulting in a certain amount of contribution to the subthreshold current even at 300 K.
Journal ArticleDOI
A 2.5-GHz four-phase clock generator with scalable no-feedback-loop architecture
TL;DR: In this paper, an accurate yet simple multiphase clock generator was developed by using a delay compensation technique based on phase interpolation that supplies a multi-phase clock signal without increasing local circuit area.