Many metal–insulator–metal systems show electrically induced resistive switching effects and have therefore been proposed as the basis for future non-volatile memories. They combine the advantages of Flash and DRAM (dynamic random access memories) while avoiding their drawbacks, and they might be highly scalable. Here we propose a coarse-grained classification into primarily thermal, electrical or ion-migration-induced switching mechanisms. The ion-migration effects are coupled to redox processes which cause the change in resistance. They are subdivided into cation-migration cells, based on the electrochemical growth and dissolution of metallic filaments, and anion-migration cells, typically realized with transition metal oxides as the insulator, in which electronically conducting paths of sub-oxides are formed and removed by local redox processes. From this insight, we take a brief look into molecular switching systems. Finally, we discuss chip architecture and scaling issues.

http://chialvo.org/Curso/UBACurso/DIA7/Papers/Aono_NatMat_07_Ionic%20Switching%20Memory.pdf

Nanoionics-based resistive switching memories

Redox‐Based Resistive Switching Memories – Nanoionic Mechanisms, Prospects, and Challenges

Bose-Einstein condensation (BEC) has been observed in a dilute gas of sodium atoms. A Bose-Einstein condensate consists of a macroscopic population of the ground state of the system, and is a coherent state of matter. In an ideal gas, this phase transition is purely quantum-statistical. The study of BEC in weakly interacting systems which can be controlled and observed with precision holds the promise of revealing new macroscopic quantum phenomena that can be understood from first principles.

Bose-Einstein condensation in a gas of sodium atoms

Memristive devices are electrical resistance switches that can retain a state of internal resistance based on the history of applied voltage and current. These devices can store and process information, and offer several key performance characteristics that exceed conventional integrated circuit technology. An important class of memristive devices are two-terminal resistance switches based on ionic motion, which are built from a simple conductor/insulator/conductor thin-film stack. These devices were originally conceived in the late 1960s and recent progress has led to fast, low-energy, high-endurance devices that can be scaled down to less than 10 nm and stacked in three dimensions. However, the underlying device mechanisms remain unclear, which is a significant barrier to their widespread application. Here, we review recent progress in the development and understanding of memristive devices. We also examine the performance requirements for computing with memristive devices and detail how the outstanding challenges could be met.

Memristive devices for computing

Despite much progress in semiconductor integrated circuit technology, the extreme complexity of the human cerebral cortex, with its approximately 10(14) synapses, makes the hardware implementation of neuromorphic networks with a comparable number of devices exceptionally challenging. To provide comparable complexity while operating much faster and with manageable power dissipation, networks based on circuits combining complementary metal-oxide-semiconductors (CMOSs) and adjustable two-terminal resistive devices (memristors) have been developed. In such circuits, the usual CMOS stack is augmented with one or several crossbar layers, with memristors at each crosspoint. There have recently been notable improvements in the fabrication of such memristive crossbars and their integration with CMOS circuits, including first demonstrations of their vertical integration. Separately, discrete memristors have been used as artificial synapses in neuromorphic networks. Very recently, such experiments have been extended to crossbar arrays of phase-change memristive devices. The adjustment of such devices, however, requires an additional transistor at each crosspoint, and hence these devices are much harder to scale than metal-oxide memristors, whose nonlinear current-voltage curves enable transistor-free operation. Here we report the experimental implementation of transistor-free metal-oxide memristor crossbars, with device variability sufficiently low to allow operation of integrated neural networks, in a simple network: a single-layer perceptron (an algorithm for linear classification). The network can be taught in situ using a coarse-grain variety of the delta rule algorithm to perform the perfect classification of 3 × 3-pixel black/white images into three classes (representing letters). This demonstration is an important step towards much larger and more complex memristive neuromorphic networks.

Training and operation of an integrated neuromorphic network based on metal-oxide memristors

Programmable devices such as SRAM-based FPGAs have the major challenges of power consumption and circuit area due to the excessive standby leakage current and the threshold voltage variation in highly scaled SRAM. Back-end-of-line (BEOL) device, which is integrated in the interconnect layers, is attractive for reducing the performance gap between FPGA and cell-based ASIC [1–4]. In this paper, we demonstrate the fundamental operations of a programmable cell array and a 32×32 crossbar switch using a nonvolatile and rewritable solid-electrolyte switch (nanobridge or NB). A 72% reduction in chip-area compared with that of a standard-cell-based design is achieved on a 90nm CMOS platform.

Programmable cell array using rewritable solid-electrolyte switch integrated in 90nm CMOS

Advanced SoC chips used in multimedia devices such as mobile phones have a number of dedicated functional IP cores, including 3D graphics and video codec, and require local memories with high bit density. Each IP core is connected to closely positioned local memories for fast access and wide bandwidth. The simultaneous operation of all of IP cores on a chip is an extremely rare situation and we anticipate that future integration of more IP cores onto a chip will increase the average number of sleeping IP cores at any given time. Therefore, current chip architectures that allocate local memories to individual IP cores will become increasingly inefficient in thier use of memory resources. In contrast to this, is the use of an off-chip external memory shared by a number of IP cores.

A chip-stacked memory for on-chip SRAM-rich SoCs and processors

We have fabricated electrically variable shallow junction metal-oxide-silicon field-effect transistors (EJ-MOSFETs) to investigate transport characteristics of ultrafine gate MOSFETs. By using EB direct writing on an ultrahigh-resolution negative resist (calixarene), we could achieved a gate length of only 14 nm. Despite such an ultrafine gate, the device exhibited transistor operation at room temperature. From studying the devices with the gate lengths from 14 nm to 98 nm, we found that when the gate length was below 30 nm the subthreshold leakage current increased. The low-temperature measurements showed that the leakage current was caused by the classical thermal process and that quantum effects do not play an important role in subthreshold characteristics at room temperature.

Transistor characteristics of 14-nm-gate-length EJ-MOSFETs

Reconfigurable nonvolatile programmable logic using complementary atom switch (CAS) is successfully demonstrated on a 65-nm-node test chip. Various logics are realized by synthesizing RTL codes and mapping the configurations into CAS-based programmable cell array. Each cell includes the two 4-input LUTs, 19×16 crossbar switch, and 368-b CAS. The CAS integrated over CMOS reduces the cell area by 78% compared to a conventional SRAM-based design.

First demonstration of logic mapping on nonvolatile programmable cell using complementary atom switch

New electron beam (EB) resists made of calixarene resists are introduced. Typical sensitivities of calixarene resists range from 700 µ C/cm2 to 7 mC/cm2. High-density dot arrays with 15 nm diameter constructed using calixarene resist were easily delineated using a point EB lithography system. Our results suggest that the resolution limit of calixarene resists is dominated by a development process such as adhesion to a substrate rather than by the EB profile. Calixarene resists are resistant to etching by halide plasma. We also demonstrated nanoscale devices processed by using calixarene resists. Calixarene resists are promising materials for nanofabrication.

Toshitsugu Sakamoto

Papers

Programmable cell array using rewritable solid-electrolyte switch integrated in 90nm CMOS

A chip-stacked memory for on-chip SRAM-rich SoCs and processors

Transistor characteristics of 14-nm-gate-length EJ-MOSFETs

First demonstration of logic mapping on nonvolatile programmable cell using complementary atom switch

Calixarene Electron Beam Resist for Nano-Lithography