Many metal–insulator–metal systems show electrically induced resistive switching effects and have therefore been proposed as the basis for future non-volatile memories. They combine the advantages of Flash and DRAM (dynamic random access memories) while avoiding their drawbacks, and they might be highly scalable. Here we propose a coarse-grained classification into primarily thermal, electrical or ion-migration-induced switching mechanisms. The ion-migration effects are coupled to redox processes which cause the change in resistance. They are subdivided into cation-migration cells, based on the electrochemical growth and dissolution of metallic filaments, and anion-migration cells, typically realized with transition metal oxides as the insulator, in which electronically conducting paths of sub-oxides are formed and removed by local redox processes. From this insight, we take a brief look into molecular switching systems. Finally, we discuss chip architecture and scaling issues.

http://chialvo.org/Curso/UBACurso/DIA7/Papers/Aono_NatMat_07_Ionic%20Switching%20Memory.pdf

Nanoionics-based resistive switching memories

Redox‐Based Resistive Switching Memories – Nanoionic Mechanisms, Prospects, and Challenges

Bose-Einstein condensation (BEC) has been observed in a dilute gas of sodium atoms. A Bose-Einstein condensate consists of a macroscopic population of the ground state of the system, and is a coherent state of matter. In an ideal gas, this phase transition is purely quantum-statistical. The study of BEC in weakly interacting systems which can be controlled and observed with precision holds the promise of revealing new macroscopic quantum phenomena that can be understood from first principles.

Bose-Einstein condensation in a gas of sodium atoms

Memristive devices are electrical resistance switches that can retain a state of internal resistance based on the history of applied voltage and current. These devices can store and process information, and offer several key performance characteristics that exceed conventional integrated circuit technology. An important class of memristive devices are two-terminal resistance switches based on ionic motion, which are built from a simple conductor/insulator/conductor thin-film stack. These devices were originally conceived in the late 1960s and recent progress has led to fast, low-energy, high-endurance devices that can be scaled down to less than 10 nm and stacked in three dimensions. However, the underlying device mechanisms remain unclear, which is a significant barrier to their widespread application. Here, we review recent progress in the development and understanding of memristive devices. We also examine the performance requirements for computing with memristive devices and detail how the outstanding challenges could be met.

Memristive devices for computing

Despite much progress in semiconductor integrated circuit technology, the extreme complexity of the human cerebral cortex, with its approximately 10(14) synapses, makes the hardware implementation of neuromorphic networks with a comparable number of devices exceptionally challenging. To provide comparable complexity while operating much faster and with manageable power dissipation, networks based on circuits combining complementary metal-oxide-semiconductors (CMOSs) and adjustable two-terminal resistive devices (memristors) have been developed. In such circuits, the usual CMOS stack is augmented with one or several crossbar layers, with memristors at each crosspoint. There have recently been notable improvements in the fabrication of such memristive crossbars and their integration with CMOS circuits, including first demonstrations of their vertical integration. Separately, discrete memristors have been used as artificial synapses in neuromorphic networks. Very recently, such experiments have been extended to crossbar arrays of phase-change memristive devices. The adjustment of such devices, however, requires an additional transistor at each crosspoint, and hence these devices are much harder to scale than metal-oxide memristors, whose nonlinear current-voltage curves enable transistor-free operation. Here we report the experimental implementation of transistor-free metal-oxide memristor crossbars, with device variability sufficiently low to allow operation of integrated neural networks, in a simple network: a single-layer perceptron (an algorithm for linear classification). The network can be taught in situ using a coarse-grain variety of the delta rule algorithm to perform the perfect classification of 3 × 3-pixel black/white images into three classes (representing letters). This demonstration is an important step towards much larger and more complex memristive neuromorphic networks.

Training and operation of an integrated neuromorphic network based on metal-oxide memristors

A resistance change element includes: a first insulating film provided on a semiconductor substrate formed on a transistor; first and second electrodes embedded in the first insulating film which supply metal ion; a second insulating film covering the first insulating film and the first and second electrodes; first and second opening portions exposing parts of an upper surface including end portions of the first and second electrodes from the second insulating film with translational symmetry; metal deposition type first and second resistance change films covering the first and second opening portions and connecting to the parts of the upper surface including the end portions of the first and second electrodes at the opening portions; third and fourth electrodes connecting to upper surfaces of the first and second resistance change films; and a fifth electrode connecting to the third and fourth electrodes and to a diffusion layer of the transistor.

Resistance change element and method of manufacturing the same and semiconductor device

We have developed a CMOS logic compatible process for embedding Cu atom switches in a Cu/low-k back-end-of-line without degrading interconnect and switch performance characteristics. The key technologies are (i) burying a via-interlayer dielectric layer between the switches without voids, followed by surface planarization using chemical mechanical polishing, and (ii) introducing a Ta protective second top electrode, which realizes simultaneous via-openings to both the switches and the lower interconnects without degrading physical morphology and electric properties of the switches. The developed process enables us to integrate the atom switches on logic with only two additional masks at low cost.

https://iopscience.iop.org/article/10.7567/JJAP.54.05ED05/pdf

Logic compatible process technology for embedded atom switches in CMOS

Progress in the Atomic Switch

The present invention provides a numerical information generation device that reduces the man hours that characterise a crossbar switch composed of a variable-resistance element. In this numerical information generation device, an input unit inputs information of a programmable logic integrated circuit including a plurality of crossbar switches each composed of a variable-resistance element. For each of the plurality of crossbar switches, a calculation unit calculates a base delay, for which the influence of the load capacity of another crossbar switch is excluded, and a correction delay, which is caused by the influence of the fan-out of the other crossbar switch. Furthermore, the calculation unit calculates a delay for each of the plurality of crossbar switches on the basis of the base delays and the correction delays respectively corresponding to the plurality of crossbar switches.

Numerical information generation apparatus, numerical information generation method, and program

A crossbar switch comprising: a first interconnect, a second interconnect, and a resistance change element. The resistance change element includes: a first electrode connected to the first interconnect and a second electrode connected to the second interconnect which are embedded in a first insulating film on a substrate having a transistor; a second insulating film covering the first insulating film and the first and second electrodes; first and second opening portions exposing parts of an upper surface including end portions of the first and second electrodes from the second insulating film with translational symmetry; first and second resistance change films covering the first and second opening portions and connecting to the first and second electrodes at the opening portions; third and fourth electrodes connecting to the first and second resistance change films; a fifth electrode connecting to the third and fourth electrodes and to a diffusion layer of the transistor.

Toshitsugu Sakamoto

Papers

Resistance change element and method of manufacturing the same and semiconductor device

Logic compatible process technology for embedded atom switches in CMOS

Progress in the Atomic Switch

Numerical information generation apparatus, numerical information generation method, and program

Crossbar switch and method of manufacturing the same and semiconductor device