Showing papers by "Tsunenobu Kimoto published in 2000"

Formation of periodic steps with a unit-cell height on 6H-SiC (0001) surface by HCl etching

Abstract: Step bunching on 6H–SiC (0001)-vicinal face etched by HCl at 1300–1500 °C is investigated by atomic force microscopy. When the substrate has the inclination toward near 〈0110〉 or even 〈1120〉, continuous parallel and periodic microsteps with six-bilayer height are laid perpendicular to the off direction, although those perpendicular to 〈1120〉 are apt to decompose into three bilayer or less. Formation mechanism of unit-cell-height steps is discussed based on consideration of bond configuration at step edges.

Traps at the SiC/SiO2-Interface

Abstract: The density of interface states Dit at SiC/SiO2 interfaces of different SiC polytypes (4H-, 6H- and 15R-SiC) is monitored and the origin of these states is discussed. The hydrogenation behavior of interface states in the temperature range from 250°C to 1000°C is studied by C-V and G-V investigations. The strong increase of Dit close to the 4H-SiC conduction band is attributed to defects located in the oxide (so-called “Near Interface Traps”).

SiC MISFETs with MBE-grown AlN gate dielectric

Abstract: Metal-Insulator-Semiconductor Field Effect Transistors (MISFETs) with ion implanted source and drain junctions have been made in 6H silicon carbide (SiC). Aluminum nitride (AlN) was used as the insulating gate dielectric, and was grown using molecular beam epitaxy (MBE). Gate controlled transistor operation was shown with an inversion layer mobility of 10-20 cm2/Vs. However, due to relaxation of the AlN film, the gate leakage was excessive, which precluded a thorough investigation of the transistor characteristics. This paper describes the manufacturing process and current voltage characteristics, and an improved process sequence is also proposed.

Pinch-off type vertical junction field effect transistor and method of manufacturing the same

Abstract: A junction field effect transistor (JFET) is provided that is capable of a high voltage resistance, high current switching operation, that operates with a low loss, and that has little variation This JFET is provided with a gate region ( 2 ) of a second conductivity type provided on a surface of a semiconductor substrate, a source region ( 1 ) of a first conductivity type, a channel region ( 10 ) of the first conductivity type that adjoins the source region, a confining region ( 5 ) of the second conductivity type that adjoins the gate region and confines the channel region, a drain region ( 3 ) of the first conductivity type provided on a reverse face, and a drift region ( 4 ) of the first conductivity type that continuously lies in a direction of thickness of the substrate from a channel to a drain A concentration of an impurity of the first conductivity type in the drift region and the channel region is lower than a concentration of an impurity of the first conductivity type in the source region and the drain region and a concentration of an impurity of the second conductivity type in the confining region

Junction field-effect transistor and method of manufacture thereof

Abstract: A low-loss junction field-effect transistor (JFET) capable of switching at high voltage and high current comprises a gate region (2) of a second conductivity type provided on the surface of a semiconductor substrate, a source region (1) of a first conductivity type, a channel region (10) of the first conductivity type extending continuously from the source region, a region (5) of the second conductivity type extending continuously from the gate region to define the channel region, a drain region (3) of the first conductivity type provided on the backside, and a drift region (4) of the first conductivity type extending continuously from the channel to the drain in the direction of the substrate thickness. The concentrations of the first conductivity type dopant in the drift region and the channel region are lower than the concentrations of the first conductivity type dopant in the source region and the drain region and the concentration of the second conductivity type dopant in the defining region.

Vanadium Ion Implanted Guard Rings for High-Voltage 4H-SiC Schottky Rectifiers

Abstract: Vanadium ion (51V+) implantation using a low dose in the range of 1012–1013 cm-2 was applied to form a high-resistivity guard ring for high-voltage 4H-SiC Schottky rectifiers. Breakdown voltages were successfully increased by the formation of a 51V+-implanted guard ring. To investigate the effects of the implanted guard ring, the width and depth were varied by the size of the mask pattern and the maximum implantation energy, respectively. With a 150 µm-wide and 0.5 µm-deep 51V+-implanted guard ring, a nearly ideal breakdown voltage of 1630 V was achieved using a 10 µm-thick epilayer.

Epitaxial Growth of SiC on Non-Typical Orientations and MOS Interfaces

Abstract: High-quality 4H-SiC has been epitaxially grown on (112¯0) substrates by chemical vapor deposition. The physical properties of epilayers and MOS interfaces on both (112¯0) and off-axis (0001) substrates are elucidated. An unintentionally doped 4H-SiC epilayer on (112¯0) shows a donor concentration of 1×1014 cm−3 with a total trap concentration as low as 3.8×1012 cm−3. Inversion-type planar MOSFETs fabricated on 4H-SiC (112¯0) exhibit a high channel mobility of 96 cm2/Vs. The channel mobility decreases according to the T−2.2 dependence above 200K, indicating reduced Coulomb scattering and/or electron trapping. The superior MOS interface on (112¯0) originates from the much lower interface state density near the conduction band edge.