An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

For more than four decades, transistors have been shrinking exponentially in size, and therefore the number of transistors in a single microelectronic chip has been increasing exponentially. Such an increase in packing density was made possible by continually shrinking the metal–oxide–semiconductor field-effect transistor (MOSFET). In the current generation of transistors, the transistor dimensions have shrunk to such an extent that the electrical characteristics of the device can be markedly degraded, making it unlikely that the exponential decrease in transistor size can continue. Recently, however, a new generation of MOSFETs, called multigate transistors, has emerged, and this multigate geometry will allow the continuing enhancement of computer performance into the next decade.

Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors

This review paper explores considerations for ultimate CMOS transistor scaling Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results

Considerations for Ultimate CMOS Scaling

A method for fabricating a semiconductor device includes forming a first fin and a second fin on a substrate. The first fin has a first gate region and the second fin has a second gate region. The method also includes forming a metal-gate line over the first and second gate regions. The metal-gate line extends from the first fin to the second fin. The method also includes applying a line-cut to separate the metal-gate line into a first sub-metal gate line and a second sub-metal gate line and forming an isolation region within the line cut.

Method of cutting metal gate

https://cyberleninka.org/article/n/1380904.pdf

ASAP7: A 7-nm finFET predictive process design kit

A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary FinFET device includes a substrate of a crystalline semiconductor material having a top surface of a first crystal plane orientation; a fin structure of the crystalline semiconductor material overlying the substrate; a gate structure over a portion of the fin structure; an epitaxy layer over another portion of the fin structure, the epitaxy layer having a surface having a second crystal plane orientation, wherein the epitaxy layer and underlying fin structure include a source and drain region, the source region being separated from the drain region by the gate structure; and a channel defined in the fin structure from the source region to the drain region, and aligned in a direction parallel to both the surface of the epitaxy layer and the top surface of the substrate.

Method of fabricating a FinFET device

An integrated circuit structure includes a fin field-effect transistor (FinFET) including a semiconductor fin over and adjacent to insulation regions; and a source/drain region over the insulation regions. The source/drain region includes a first and a second semiconductor region. The first semiconductor region includes silicon and an element selected from the group consisting of germanium and carbon, wherein the element has a first atomic percentage in the first semiconductor region. The first semiconductor region has an up-slant facet and a down-slant facet. The second semiconductor region includes silicon and the element. The element has a second atomic percentage lower than the first atomic percentage. The second semiconductor region has a first portion on the up-slant facet and has a first thickness. A second portion of the second semiconductor region, if any, on the down-slant facet has a second thickness smaller than the first thickness.

Controlling the shape of source/drain regions in FinFETs

A high performance 22/20nm CMOS bulk FinFET achieves the best in-class N/P I on values of 1200/1100 µA/µm for I off =100nA/µm at 1V. Excellent device electrostatic control is demonstrated for gate length (L gate ) down to 20nm. Dual-Epitaxy and multiple stressors are essential to boost the device performance. Dual workfunction (WF) with an advanced High-K/Metal gate (HK/MG) stack is deployed in an integration-friendly CMOS process flow. This dual-WF approach provides excellent V th roll-off immunity in the short-channel regime that allows properly positioning the long-channel device V th . Enhanced 193nm immersion lithography has enabled the stringent requirements of the 22/20nm ground rules. Reliability of our advanced HK/MG stack is promising. Excellent SRAM static noise margin at 0.45V is reported.

High performance 22/20nm FinFET CMOS devices with advanced high-K/metal gate scheme

A method of forming an integrated circuit structure includes providing a wafer including a substrate and a semiconductor fin at a major surface of the substrate, and performing a deposition step to epitaxially grow an epitaxy layer on a top surface and sidewalls of the semiconductor fin, wherein the epitaxy layer includes a semiconductor material. An etch step is then performed to remove a portion of the epitaxy layer, with a remaining portion of the epitaxy layer remaining on the top surface and the sidewalls of the semiconductor fin.

Epitaxy profile engineering for FinFETs

An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides a processing for forming improved lightly doped source/drain features and source/drain features in the semiconductor device. Semiconductor device with the improved lightly doped source/drain features and source/drain features may prevent or reduce defects and achieve high strain effect. In at least one embodiment, the lightly doped source/drain features and source/drain features comprises the same semiconductor material formed by epitaxial growth.

Tsz-Mei Kwok

Papers

Method of fabricating a FinFET device

Controlling the shape of source/drain regions in FinFETs

High performance 22/20nm FinFET CMOS devices with advanced high-K/metal gate scheme

Epitaxy profile engineering for FinFETs

Method of manufacturing strained source/drain structures