Huan-Just Lin

TL;DR: In this article, a 22/20nm CMOS bulk FinFET with dual workfunction (WF) with an advanced High-K/Metal gate (HK/MG) stack is deployed in an integration-friendly CMOS process flow.

TL;DR: A gas distribution system for improving asymmetric etching and deposition control over a substrate diameter in a plasma reactor including a plasminar chamber further including a substrate holder for holding a substrate surface disposed in a lower portion of said plasma reactor.

TL;DR: In this paper, a dual-metal gate stack is used for semiconductor devices with a first and a second doped region separated by an insulation layer, and a sealing layer is disposed on the sidewalls of the first gate stack and the second gate stack.

TL;DR: In this paper, a process for forming very narrow polysilicon gate lines for use as gate electrodes in FETs is described, which uses a consumable hard mask of silicon oxynitride covered by a thin layer of silicon oxide during the etching of the poly-silicon.

TL;DR: In this article, an integrated circuit having an improved gate contact and a method of making the circuit are provided. In an exemplary embodiment, the method includes receiving a substrate, which includes a gate stack disposed on the substrate and an interlayer dielectric disposed in the gate stack.