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Chuan-Ping Hou
Researcher at TSMC
Publications - 6
Citations - 260
Chuan-Ping Hou is an academic researcher from TSMC. The author has contributed to research in topics: Layer (electronics) & CMOS. The author has an hindex of 5, co-authored 6 publications receiving 219 citations.
Papers
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Proceedings ArticleDOI
High performance 22/20nm FinFET CMOS devices with advanced high-K/metal gate scheme
C. C. Wu,Derek Lin,A. Keshavarzi,C.H. Huang,C.T. Chan,Tseng Chien-Hsien,Chun Chen,Hsieh Ching-Hua,King-Yuen Wong,M.L. Cheng,T.H. Li,Y.C. Lin,L.Y. Yang,C. P. Lin,Chuan-Ping Hou,H. C. Lin,J.L. Yang,K. F. Yu,Ming-Jer Chen,T.H. Hsieh,Y. C. Peng,Chou Chun-Hao,Lee Chia-Fu,Chien-Chao Huang,Chih-Yuan Lu,F.K. Yang,Huan-Neng Chen,L.W. Weng,P.C. Yen,Wang Shiang-Bau,Stock Chang,S.W. Chuang,T.C. Gan,Tzong-Lin Wu,Tsung-Lin Lee,W.S. Huang,Yi-Chun Huang,Y.W. Tseng,C.M. Wu,Eric Ou-Yang,K.Y. Hsu,L.T. Lin,S.B. Wang,Tsz-Mei Kwok,Chien-Chang Su,C.H. Tsai,Ming-Jie Huang,Huan-Just Lin,A.S. Chang,S.H. Liao,Li-Shiun Chen,J.H. Chen,P.S. Lim,X.F. Yu,S.Y. Ku,Yung-Huei Lee,P.C. Hsieh,Po-Kang Wang,Yuan-Hung Chiu,S.S. Lin,Hun-Jan Tao,M. Cao,Yuh-Jier Mii +62 more
TL;DR: In this article, a 22/20nm CMOS bulk FinFET with dual workfunction (WF) with an advanced High-K/Metal gate (HK/MG) stack is deployed in an integration-friendly CMOS process flow.
Proceedings ArticleDOI
5nm CMOS Production Technology Platform featuring full-fledged EUV, and High Mobility Channel FinFETs with densest 0.021µm 2 SRAM cells for Mobile SoC and High Performance Computing Applications
Geoffrey Yeap,X. Chen,B. R. Yang,C. P. Lin,F. C. Yang,Y. K. Leung,Derek Lin,C. P. Chen,K. F. Yu,D. H. Chen,Chun-Yen Chang,S.S. Lin,Huan-Neng Chen,P. Hung,Chuan-Ping Hou,Cheng Yun-Wei,Jonathan Chang,L. Yuan,Chung-Kai Lin,Chun-Kuang Chen,Yee-Chia Yeo,Ming-Huan Tsai,Yung-Shun Chen,Hsien-Chin Lin,C. O. Chui,Kevin Huang,W. Chang,Hon-Jarn Lin,Kuang-Hsin Chen,R. Chen,S. H. Sun,Q. Fu,H. T. Yang,H. L. Shang,H. T. Chiang,C. C. Yeh,Tze-Liang Lee,C. H. Wang,S. L. Shue,C. W. Wu,Ryan Lu,Wei-Heng Lin,Jau-Yi Wu,F. L. Lai,Po-Kang Wang,Yung-Hsien Wu,B. Z. Tien,Y. C. Huang,L. C. Lu,Jun He,Y. Ku,Jing-Cheng Lin,M. Cao,T. S. Chang,S. M. Jang,H. C. Lin,Yung-Chow Peng,Jyh-Cherng Sheu,Ming-Fang Wang +58 more
TL;DR: The 5nm platform technology successfully passed qualification with consistently high yielding 256Mb HD/HC SRAM, and large logic test chip consisting of CPU/GPU/SoC blocks, on schedule for high volume production in 1H 2020.
Proceedings ArticleDOI
A 65nm node strained SOI technology with slim spacer
Fu-Liang Yang,Chien-Chao Huang,Hou-Yu Chen,Jhon-Jhy Liaw,Tang-Xuan Chung,Hung-Wei Chen,Chang-Yun Chang,Cheng Chuan Huang,Kuang-Hsin Chen,Di-Hong Lee,Hsun-Chih Tsao,Cheng-Kuo Wen,Shui-Ming Cheng,Yi-Ming Sheu,Ke-Wei Su,Chi-Chun Chen,Tze-Liang Lee,Shih-Chang Chen,C.H. Chen,Cheng-hung Chang,Jhi-cheng Lu,W. Chang,Chuan-Ping Hou,Ying-Ho Chen,Kuei-Shun Chen,Ming Lu,Li-Wei Kung,Yu-Jun Chou,Fu-Jye Liang,Jan-Wen You,King-Chang Shu,Bin-Chang Chang,Jaw-Jung Shin,Chun-Kuang Chen,Tsai-Sheng Gau,Bor-Wen Chan,Yi-Chun Huang,Han-Jan Tao,J.H. Chen,Yung-Shun Chen,Yee-Chia Yeo,Samuel Fung,Carlos H. Diaz,Chii-Ming Wu,Burn-Jeng Lin,Liang Min-Chang,J.Y.-C. Sun,Chenming Hu +47 more
TL;DR: In this article, a 65 nm node strained SOI technology with high performance is demonstrated, providing drive currents of 1015 and 500 /spl mu/A/A//spl µ/m for N-FETs and P-Fet, respectively, at an off-state leakage of 40 nA/spl μ/m using 1 V operation.
Patent
STI liner for SOI structure
TL;DR: In this article, the patterned silicon layer is removed with an etching process, such that a sidewall portion of the Patterned Silicon Layer is exposed and such that the remaining portion remains at a corner where the patterning silicon layer interfaces with the buried insulator layer.
Patent
FIN-FET device structure formed employing bulk semiconductor substrate
Kuang-Hsin Chen,Hsun-Chih Tsao,Jhi-Cherng Lu,Chuan-Ping Hou,Peng-Fu Hsu,Hung-Wei Chen,Di-Hong Lee +6 more
TL;DR: A fin-FET device and a method for fabrication thereof both employ a bulk semiconductor substrate as mentioned in this paper, where a fin and an adjoining trough are formed within the bulk semiconducting substrate.