M
Ming-Jie Huang
Researcher at TSMC
Publications - 6
Citations - 249
Ming-Jie Huang is an academic researcher from TSMC. The author has contributed to research in topics: Etching (microfabrication) & Logic gate. The author has an hindex of 6, co-authored 6 publications receiving 244 citations.
Papers
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Proceedings ArticleDOI
High performance 22/20nm FinFET CMOS devices with advanced high-K/metal gate scheme
C. C. Wu,Derek Lin,A. Keshavarzi,C.H. Huang,C.T. Chan,Tseng Chien-Hsien,Chun Chen,Hsieh Ching-Hua,King-Yuen Wong,M.L. Cheng,T.H. Li,Y.C. Lin,L.Y. Yang,C. P. Lin,Chuan-Ping Hou,H. C. Lin,J.L. Yang,K. F. Yu,Ming-Jer Chen,T.H. Hsieh,Y. C. Peng,Chou Chun-Hao,Lee Chia-Fu,Chien-Chao Huang,Chih-Yuan Lu,F.K. Yang,Huan-Neng Chen,L.W. Weng,P.C. Yen,Wang Shiang-Bau,Stock Chang,S.W. Chuang,T.C. Gan,Tzong-Lin Wu,Tsung-Lin Lee,W.S. Huang,Yi-Chun Huang,Y.W. Tseng,C.M. Wu,Eric Ou-Yang,K.Y. Hsu,L.T. Lin,S.B. Wang,Tsz-Mei Kwok,Chien-Chang Su,C.H. Tsai,Ming-Jie Huang,Huan-Just Lin,A.S. Chang,S.H. Liao,Li-Shiun Chen,J.H. Chen,P.S. Lim,X.F. Yu,S.Y. Ku,Yung-Huei Lee,P.C. Hsieh,Po-Kang Wang,Yuan-Hung Chiu,S.S. Lin,Hun-Jan Tao,M. Cao,Yuh-Jier Mii +62 more
TL;DR: In this article, a 22/20nm CMOS bulk FinFET with dual workfunction (WF) with an advanced High-K/Metal gate (HK/MG) stack is deployed in an integration-friendly CMOS process flow.
Proceedings ArticleDOI
A 25-nm gate-length FinFET transistor module for 32nm node
C.H. Chang,Tsung-Lin Lee,Clement Hsingjen Wann,Li-Shyue Lai,Hung-Ming Chen,Chih-Chieh Yeh,Chih-Sheng Chang,Chia-Cheng Ho,Jyh-Cherng Sheu,Tsz-Mei Kwok,Feng Yuan,Shao-Ming Yu,Chia-Feng Hu,Jeng-Jung Shen,Yi-Hsuan Liu,Chen-Ping Chen,Shin-Chih Chen,Li-Shiun Chen,Leo Chen,Yuan-Hung Chiu,Chu-Yun Fu,Ming-Jie Huang,Yu-Lien Huang,Shih-Ting Hung,Jhon-Jhy Liaw,Hsien-Chin Lin,Hsien-Hsin Lin,Li-Te Lin,Shyue-Shyh Lin,Yuh-Jier Mii,Eric Ou-Yang,Ming-Feng Shieh,Chien-Chang Su,Shih-Peng Tai,Hun-Jan Tao,Ming-Huan Tsai,Kai-Ting Tseng,Kin-Weng Wang,Wang Shiang-Bau,Jeff J. Xu,Fu-Kai Yang,Shu-Tine Yang,Chen-Nan Yeh +42 more
TL;DR: A high-performance and low-power FinFET module at 25 nm gate length that can be readily traded with VDD scaling for low power and superior electrostatics and reduced random dopant fluctuation.
Patent
Method using wet etching to trim a critical dimension
TL;DR: In this paper, a method for using an isotropic wet etching process chemical process for trimming semiconductor feature sizes with improved critical dimension control including providing a hard mask overlying a substrate included in a semiconductor wafer, is presented.
Patent
Method of manufacturing source/drain structures
TL;DR: In this article, an integrated circuit device and method for manufacturing the integrated circuit devices provide improved control over a shape of a trench for forming the source and drain features of integrated circuits by forming a second doped region in a first doped regions and removing the first and the second regions by a first and a second wet etching processes.
Patent
Large-scale trimming for ultra-narrow gates
TL;DR: In this paper, large-scale trimming for forming ultra-narrow gates for semiconductor devices is disclosed, where a hard mask layer is trimmed to further narrow the width of the hard mask, where the soft mask layer has been removed.