T
Tze-Chiang Chen
Researcher at IBM
Publications - 36
Citations - 834
Tze-Chiang Chen is an academic researcher from IBM. The author has contributed to research in topics: Layer (electronics) & Transistor. The author has an hindex of 10, co-authored 36 publications receiving 811 citations. Previous affiliations of Tze-Chiang Chen include GlobalFoundries.
Papers
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Journal ArticleDOI
Efficient and bright organic light-emitting diodes on single-layer graphene electrodes
Ning Li,Satoshi Oida,George S. Tulevski,Shu-Jen Han,James B. Hannon,Devendra K. Sadana,Tze-Chiang Chen +6 more
TL;DR: Single-layer graphene is used as an alternative flexible transparent conductor, yielding white organic light-emitting diodes with brightness and efficiency sufficient for general lighting and comparable to the most efficient lighting technologies.
Patent
Silicon-on-insulator vertical array device trench capacitor DRAM
Carl J. Radens,Gary B. Bronner,Tze-Chiang Chen,Bijan Davari,Jack A. Mandelman,Dan Moy,Devendra K. Sadana,Ghavam G. Shahidi,Scott R. Stiffler +8 more
TL;DR: In this article, the authors describe a DRAM cell with a trench storage capacitor connected by a self-aligned buried strap to a vertical access transistor, which is used to isolate and define cells.
Patent
Structure and method for producing low leakage isolation devices
Hiroyuki Akatsu,Tze-Chiang Chen,Laertis Economikos,Herbert L. Ho,Richard L. Kleinhenz,Jack A. Mandelman,Natsul Wesley C +6 more
TL;DR: A shallow trench isolation structure for a semiconductor device and the method for manufacturing the shallow-trench isolation device within the semiconductor substrate is described in this article. But the method is not suitable for the case where the isolation structure may include a silicon nitride liner which is within the trench and recessed below the surface.
Patent
Double SOI device with recess etch and epitaxy
Fariborz Assaderaghi,Tze-Chiang Chen,K. Muller,Edward J. Nowak,Devendra K. Sadana,Ghavam G. Shahidi +5 more
TL;DR: In this article, a groundplane SOI device consisting of at least a field effect transistor formed on a top Si-containing surface of a silicon-on-insulator (SOI) wafer is presented.
Patent
Method for fabricating SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) substrates
TL;DR: A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GON substrate materials of the present invention are provided in this article.