V
Veit B. Kleeberger
Researcher at Infineon Technologies
Publications - 30
Citations - 300
Veit B. Kleeberger is an academic researcher from Infineon Technologies. The author has contributed to research in topics: Fault injection & Resilience (network). The author has an hindex of 10, co-authored 30 publications receiving 291 citations. Previous affiliations of Veit B. Kleeberger include Technische Universität München.
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Proceedings ArticleDOI
Predicting future product performance: modeling and evaluation of standard cells in FinFET technologies
TL;DR: This paper presents an approach which is able to find the optimal sizing of basic circuit blocks considering process variation, and utilizes this approach to predict the impact of scaling in FinFET technologies and the influence of process variations in future technology nodes.
Journal ArticleDOI
A compact model for NBTI degradation and recovery under use-profile variations and its application to aging analysis of digital integrated circuits
TL;DR: A model for NBTI degradation and recovery based on trapping/detrapping is developed which accurately describes the relaxation during detrapping, the quasi-permanent degradation and shows good agreement with measurements from a 65 nm technology.
Journal ArticleDOI
Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience
Andreas Herkersdorf,Hananeh Aliee,Michael Engel,Michael Glaß,Christina Gimmler-Dumont,Jorg Henkel,Veit B. Kleeberger,Michael A. Kochte,Johannes Maximilian Kühn,Daniel Mueller-Gritschneder,Sani R. Nassif,Holm Rauchfuss,Wolfgang Rosenstiel,Ulf Schlichtmann,Muhammad Shafique,Mehdi B. Tahoori,Jürgen Teich,Norbert Wehn,Christian Weis,Hans-Joachim Wunderlich +19 more
TL;DR: This paper shows by example how probabilistic bit flips are systematically abstracted and propagated towards higher abstraction levels up to the application software layer, and how RAP can be used to parameterize architecture-level resilience methods.
Journal ArticleDOI
A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience
Veit B. Kleeberger,Christina Gimmler-Dumont,Christian Weis,Andreas Herkersdorf,Daniel Mueller-Gritschneder,Sani R. Nassif,Ulf Schlichtmann,Norbert Wehn +7 more
TL;DR: This article illustrates a methodology for dealing with scaling- related problems via two case studies that link models of low-level technology-related problems to system behavior, which spreads the burden of ensuring resilience across multiple levels of the design hierarchy.
Proceedings ArticleDOI
Workload- and Instruction-Aware Timing Analysis: The missing Link between Technology and System-level Resilience
TL;DR: An enhanced static timing analysis is presented which links technology-level effects to system-level and vice versa and discusses the accurate and efficient consideration of system workload and impact of executed instructions on circuit timing.