V
Vinod Narayanan
Researcher at IBM
Publications - 14
Citations - 843
Vinod Narayanan is an academic researcher from IBM. The author has contributed to research in topics: Static timing analysis & Noise (radio). The author has an hindex of 11, co-authored 14 publications receiving 839 citations.
Papers
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Proceedings ArticleDOI
Noise in deep submicron digital design
TL;DR: Noise as it pertains to digital systems is defined and a metric referred to as noise stability is defined, and a static noise analysis methodology based on this metric is introduced to demonstrate how noise can be analyzed systematically.
Journal ArticleDOI
Harmony: static noise analysis of deep submicron digital integrated circuits
TL;DR: A metric for noise immunity is defined, and a static noise analysis methodology based on this noise-stability metric is introduced to demonstrate how noise can be analyzed systematically on a full-chip basis using simulation-based transistor-level analysis.
Proceedings ArticleDOI
Global harmony: coupled noise analysis for full-chip RC interconnect networks
TL;DR: A reduced-order modelling approach that allows for passive multiport reduction of RC netlists as impedance macromodels while preserving the symmetry and sparsity of the state matrices for efficient storage is described.
Journal ArticleDOI
Conquering noise in deep-submicron digital ICs
TL;DR: A verification metric, noise stability, which guarantees functionality in the presence of noise, and a CAD technique, static noise analysis, for applying this metric on a chipwide basis are described.
Patent
Method and apparatus for synthesizing and optimizing control logic based on SRCMOS logic array macros
Michael P. Beakes,Barbara Alana Chappell,Terry I. Chappell,Gary S. Ditlow,Barry Lee Dorfman,Bruce M. Fleischer,Vinod Narayanan,Robert Alan Philhower,George Anthony Sai Halasz,Ghavam G. Shahidi,David J. Widiger +10 more
TL;DR: In this article, a computer-based method automatically synthesizes, optimizes and compiles high performance control logic using SRCMOS LOGIC ARRAY MACROS, abbreviated as SLAMs.