W
W.H. Chang
Researcher at IBM
Publications - 4
Citations - 234
W.H. Chang is an academic researcher from IBM. The author has contributed to research in topics: CMOS & Ring oscillator. The author has an hindex of 4, co-authored 4 publications receiving 234 citations.
Papers
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Journal ArticleDOI
A high-performance 0.25- mu m CMOS technology. II. Technology
Bijan Davari,W.H. Chang,K.E. Petrillo,C.Y. Wong,D. Moy,Yuan Taur,M.R. Wordeman,J.Y.-C. Sun,C.C.-H. Hsu,M.R. Polcari +9 more
TL;DR: In this paper, a dual poly gate is fabricated using a process where the poly and source/drain (S/D) are doped simultaneously, and a reduced operating voltage of 2.5 V is used which allows the application of shallow junctions with abrupt profiles (no LDD) to minimize the device series resistance as well as gate to source/Drain overlap capacitance.
Journal ArticleDOI
A high-performance 0.25- mu m CMOS technology. I. Design and characterization
TL;DR: In this paper, a high-performance 0.25-mu m-channel CMOS technology is designed and characterized, which utilizes n/sup+/ polysilicon gates on nFETs and p/sup +/polysilicon gate on pFET, so that both FETs are surface channel devices.
Proceedings ArticleDOI
A high performance 0.25 mu m CMOS technology
Bijan Davari,W.H. Chang,M.R. Wordeman,C.S. Oh,Yuan Taur,Karen Petrillo,Dan Moy,J.J. Bucchignano,H. Ng,M. G. Rosenfield,F. J. Hohn,M. Rodriguez +11 more
TL;DR: In this article, a high performance 0.25-mu m CMOS (complementary metal oxide semiconductor) technology with a reduced operating voltage of 2.5 V is presented.
Journal ArticleDOI
Voltage dependence of the MOSFET gate-to-source/drain overlap
TL;DR: In this paper, a methode de mesure avec la jonction S/D polarisee en inverse is proposed, which peut changer par 30% ou plus durant le fonctionnement normal d'un MOSFET.