High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

Concern about the performance of wires wires in scaled technologies has led to research exploring other communication methods. This paper examines wire and gate delays as technologies migrate from 0.18-/spl mu/m to 0.035-/spl mu/m feature sizes to better understand the magnitude of the the wiring problem. Wires that shorten in length as technologies scale have delays that either track gate delays or grow slowly relative to gate delays. This result is good news since these "local" wires dominate chip wiring. Despite this scaling of local wire performance, computer-aided design (CAD) tools must still become move sophisticated in dealing with these wires. Under scaling, the total number of wires grows exponentially, so CAD tools will need to handle an ever-growing percentage of all the wires in order to keep designer workloads constant. Global wires present a more serious problem to designers. These are wires that do not scale in length since they communicate signals across the chip. The delay of these wives will remain constant if repeaters are used meaning that relative to gate delays, their delays scale upwards. These increased delays for global communication will drive architectures toward modular designs with explicit global latency mechanisms.

The future of wires

A memristor is a resistive device with an inherent memory. The theoretical concept of a memristor was connected to physically measured devices in 2008 and since then there has been rapid progress in the development of such devices, leading to a series of recent demonstrations of memristor-based neuromorphic hardware systems. Here, we evaluate the state of the art in memristor-based electronics and explore where the future of the field lies. We highlight three areas of potential technological impact: on-chip memory and storage, biologically inspired computing and general-purpose in-memory computing. We analyse the challenges, and possible solutions, associated with scaling the systems up for practical applications, and consider the benefits of scaling the devices down in terms of geometry and also in terms of obtaining fundamental control of the atomic-level dynamics. Finally, we discuss the ways we believe biology will continue to provide guiding principles for device innovation and system optimization in the field. This Perspective evaluates the state of the art in memristor-based electronics and explores the future development of such devices in on-chip memory, biologically inspired computing and general-purpose in-memory computing.

The future of electronics based on memristive systems

The development of silicon semiconductor technology has produced breakthroughs in electronics—from the microprocessor in the late 1960s to early 1970s, to automation, computers and smartphones—by downscaling the physical size of devices and wires to the nanometre regime. Now, graphene and related two-dimensional (2D) materials offer prospects of unprecedented advances in device performance at the atomic limit, and a synergistic combination of 2D materials with silicon chips promises a heterogeneous platform to deliver massively enhanced potential based on silicon technology. Integration is achieved via three-dimensional monolithic construction of multifunctional high-rise 2D silicon chips, enabling enhanced performance by exploiting the vertical direction and the functional diversification of the silicon platform for applications in opto-electronics and sensing. Here we review the opportunities, progress and challenges of integrating atomically thin materials with silicon-based nanosystems, and also consider the prospects for computational and non-computational applications. Progress in integrating atomically thin two-dimensional materials with silicon-based technology is reviewed, together with the associated opportunities and challenges, and a roadmap for future applications is presented.

Graphene and two-dimensional materials for silicon technology.

Neuromorphic computing has come to refer to a variety of brain-inspired computers, devices, and models that contrast the pervasive von Neumann computer architecture This biologically inspired approach has created highly connected synthetic neurons and synapses that can be used to model neuroscience theories as well as solve challenging machine learning problems The promise of the technology is to create a brain-like ability to learn and adapt, but the technical challenges are significant, starting with an accurate neuroscience model of how the brain works, to finding materials and engineering breakthroughs to build devices to support these models, to creating a programming framework so the systems can learn, to creating applications with brain-like capabilities In this work, we provide a comprehensive survey of the research and motivations for neuromorphic computing over its history We begin with a 35-year review of the motivations and drivers of neuromorphic computing, then look at the major research areas of the field, which we define as neuro-inspired models, algorithms and learning approaches, hardware and devices, supporting systems, and finally applications We conclude with a broad discussion on the major research topics that need to be addressed in the coming years to see the promise of neuromorphic computing fulfilled The goals of this work are to provide an exhaustive review of the research conducted in neuromorphic computing since the inception of the term, and to motivate further work by illuminating gaps in the field where new research is needed

A Survey of Neuromorphic Computing and Neural Networks in Hardware.

In this paper, the impact of fin number on device performance and hot carrier induced device degradation was investigated for n-channel tri-gate multi-fin FinFET with different fin numbers. The threshold voltage (VTH) shift, transconductance, and subthreshold swing degradation were extracted to determine the degradation of device. It was found that the device with fewer fins shows better device performance, but suffer from more serious hot carrier induced device degradation. It is suggested that the existed coupling effect between the fins reduces the equivalent electric field in the multi-fins devices, thus shows better reliability than the single-fin device does after hot carrier stress.

The impact of fin number on device's performance and reliability in tri-gate FinFETs

In this brief, nonvolatile memory (NVM) devices, based on the capacitor structure with the graphene nanosheets (GNSs) as the discrete charge storage media and atomic-layer-deposited (ALD) Al2O3 dielectric as the blocking oxide (BO) layer, have been demonstrated. The GNSs are formed by using the gold (Au) nanoparticles as the self-aligned mask and functionalized by using the NH3 plasma to enrich the charge trapping centers. In addition, the ALD Al2O3 layer is adopted as the BO layer of the GNS NVMs, resulting in a damage-free deposition on GNSs, compared to the conventional chemical-vapor-deposited SiO2 layer. The GNS NVM devices with a 15-nm-thick ALD Al2O3 BO layer can exhibit an excellent endurance of more than 105 cycles and superior data retention of lower than 30% charge loss for 10 years, suitable for future NVM applications.

Damage-Free ALD Blocking Oxide Layer on Functionalized Graphene Nanosheets as Nonvolatile Memories

Effect of Gate Capping Configurations and Silicon-on-Insulator Thickness with External Stresses on Partially Depleted MOSFETs

We introduce a single-grain gate-all-around (GAA) Si nanowire (NW) FET using the location-controlled-grain technique and several innovative low-thermal budget processes, including green nanosecond laser crystallization, far-infrared laser annealing, and hybrid laser-assisted salicidation, that keep the substrate temperature (Tsub) lower than 400 °C for monolithic three-dimensional integrated circuits (3D-ICs). The detailed process verification of a low-defect GAA nanowire and electrical characteristics were investigated in this article. The GAA Si NW FETs, which were intentionally fabricated within the controlled Si grain, exhibit a steeper subthreshold swing (S.S.) of about 65 mV/dec., higher driving currents of 327 µA/µm (n-type) and 297 µA/µm (p-type) @ Vth ± 0.8 V, and higher Ion/Ioff (>105 @|Vd| = 1 V) and have a narrower electrical property distribution. In addition, the proposed Si NW FETs with a GAA structure were found to be less sensitive to Vth roll-off and S.S. degradation compared to the omega(Ω)-gate Si FETs. It enables ultrahigh-density sequentially stackable integrated circuits with superior performance and low power consumption for future mobile and neuromorphic applications.

https://www.mdpi.com/2072-666X/11/8/741/pdf

Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional Integrated Circuits

The monostable---bistable transition logic element (MOBILE) is a promising application for negative differential resistance (NDR) circuit. Previously reported MOBILE is constructed by resonant tunneling diode (RTD) that is implemented by the molecular beam epitaxy (MBE) process. However in this paper, we first propose a NDR circuit composed of standard Si-based metal---oxide---semiconductor field-effect transistor (MOS) and SiGe-based heterojunction bipolar transistor (HBT). Then we demonstrate the inverter, NAND, and NOR gate operations using this MOS---HBT---NDR-based MOBILE circuit. The great advantage of this NDR-based application is that we can implement it using the standard SiGe BiCMOS process without the need for the MBE system.

Wen-Kuan Yeh

Papers

The impact of fin number on device's performance and reliability in tri-gate FinFETs

Damage-Free ALD Blocking Oxide Layer on Functionalized Graphene Nanosheets as Nonvolatile Memories

Effect of Gate Capping Configurations and Silicon-on-Insulator Thickness with External Stresses on Partially Depleted MOSFETs

Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional Integrated Circuits

Design of monostable---bistable transition logic element using the BiCMOS-based negative differential resistance circuit