S
S. Samavedam
Researcher at Freescale Semiconductor
Publications - 30
Citations - 1042
S. Samavedam is an academic researcher from Freescale Semiconductor. The author has contributed to research in topics: High-κ dielectric & Metal gate. The author has an hindex of 16, co-authored 30 publications receiving 1027 citations.
Papers
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Journal ArticleDOI
Fermi-level pinning at the polysilicon/metal-oxide interface-Part II
Christopher C. Hobbs,L. R. C. Fonseca,A. Knizhnik,V. Dhandapani,S. Samavedam,William J. Taylor,J. M. Grant,L. Dip,D. Triyoso,Rama I. Hegde,David C. Gilmer,R. Garcia,D. Roan,M.L. Lovejoy,Raghaw S. Rai,E. A. Hebert,Hsing-Huang Tseng,S.G.H. Anderson,Bruce E. White,Philip J. Tobin +19 more
TL;DR: In this article, it was shown that Fermi-pinning at the polysilicon/metal-oxide interface causes high threshold voltages in MOSFET devices.
Proceedings ArticleDOI
Fermi level pinning at the polySi/metal oxide interface
Chris Hobbs,L. R. C. Fonseca,V. Dhandapani,S. Samavedam,B. Taylor,John M. Grant,L. Dip,Dina H. Triyoso,Rama I. Hegde,David Gilmer,R. Garcia,D. Roan,L. Lovejoy,R. Rai,L. Hebert,H.-H. Tseng,Bruce E. White,Philip J. Tobin +17 more
TL;DR: In this article, the first time that Fermi pinning at the polySi/metal oxide interface causes high threshold voltages in MOSFET devices was reported. But the authors did not consider the effect of the interfacial Si-Hf and Si-O-Al bonds.
Proceedings ArticleDOI
A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process
X. Chen,S. Samavedam,Vijay Narayanan,Kenneth J. Stein,C. Hobbs,Christopher V. Baiocco,Weipeng Li,Jaeger Daniel,M. Zaleski,Haining Yang,Nam-Sung Kim,Yi-Wei Lee,Da Zhang,Laegu Kang,J. Chen,Haoren Zhuang,Arifuzzaman (Arif) Sheikh,J. Wallner,Michael V. Aquilino,Jin-Ping Han,Zhenrong Jin,James Chingwei Li,G. Massey,S. Kalpat,Rashmi Jha,Naim Moumen,R. Mo,S. Kirshnan,X. Wang,Michael P. Chudzik,M. Chowdhury,Deleep R. Nair,C. Reddy,Young Way Teh,Chandrasekharan Kothandaraman,Douglas D. Coolbaugh,Shesh Mani Pandey,D. Tekleab,Aaron Thean,Melanie J. Sherony,Craig S. Lage,J. Sudijono,R. Lindsay,JiYeon Ku,Mukesh Khare,An L. Steegen +45 more
TL;DR: In this article, a 32 nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 mum2 was demonstrated.
Proceedings ArticleDOI
Challenges for the integration of metal gate electrodes
James K. Schaeffer,C. Capasso,L. R. C. Fonseca,S. Samavedam,David C. Gilmer,Yong Liang,S. Kalpat,B. Adetutu,Hsing-Huang Tseng,Y. Shiho,Alexander A. Demkov,Rama I. Hegde,W.J. Taylor,Rich Gregory,J. Jiang,E. Luckowski,M. Raymond,K. Moore,Dina H. Triyoso,D. Roan,B. E. White,Philip J. Tobin +21 more
TL;DR: In this article, the integration challenges for metal gate electrodes including the presence of Fermi level pinning and the impact of interface chemistry on the effective metal work function are discussed.
Proceedings Article
High performance 32nm SOI CMOS with high-k/metal gate and 0.149µm 2 SRAM and ultra low-k back end with eleven levels of copper
Brian J. Greene,Q. Liang,K. Amarnath,Y. Wang,J. Schaeffer,M. Cai,Yue Liang,S. Saroop,J. Cheng,A. Rotondaro,Shu-Jen Han,R. Mo,K. McStay,S.H. Ku,R. Pal,Mahender Kumar,B. Dirahoui,B. Yang,F. Tamweber,Woo-Hyeong Lee,M. Steigerwalt,H. Weijtmans,Judson R. Holt,L. Black,S. Samavedam,M. Turner,K. Ramani,D. Lee,Michael P. Belyansky,M. Chowdhury,D. Aime,B. Min,H. van Meer,Haizhou Yin,K.K. Chan,M. Angyal,M. Zaleski,O. Ogunsola,C. Child,L. Zhuang,H. Yan,D. Permanaa,Jeffrey W. Sleight,Dechao Guo,S. Mittl,D. Ioannou,Ernest Y. Wu,Michael P. Chudzik,D.-G. Park,D. Brown,Scott Luning,Dan Mocuta,Edward P. Maciejewski,K. Henson,Effendi Leobandung +54 more
TL;DR: In this paper, a 32 nm SOI CMOS technology featuring high-k/metal gate and an SRAM cell size of 0.149 µm2 is presented, enabling performance without the power penalty from gate capacitance.