S
S. Dakshina-Murthy
Researcher at Motorola
Publications - 6
Citations - 214
S. Dakshina-Murthy is an academic researcher from Motorola. The author has contributed to research in topics: High-κ dielectric & Gate dielectric. The author has an hindex of 6, co-authored 6 publications receiving 211 citations.
Papers
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Journal ArticleDOI
Physical and electrical properties of metal gate electrodes on HfO2 gate dielectrics
J. K. Schaeffer,S. B. Samavedam,David Gilmer,V. Dhandapani,Philip J. Tobin,J. Mogab,Bich-Yen Nguyen,B. E. White,S. Dakshina-Murthy,Raj Rai,Z. X. Jiang,Ryan Martin,Mark V. Raymond,M. Zavala,L. B. La,J. A. Smith,R. Garcia,D. Roan,M. Kottke,Rich Gregory +19 more
TL;DR: In this article, the authors evaluated the performance of metal-oxide-semiconductor field effect transistor (MOSFET) gate lengths for the dual-metal gate complementary metaloxide semiconductor using HfO2 as the gate dielectric.
Proceedings ArticleDOI
Dual-metal gate CMOS with HfO 2 gate dielectric
Srikanth B. Samavedam,L.B. La,James Nelson Smith,S. Dakshina-Murthy,E. Luckowski,J. Schaeffer,M. Zavala,Ryan Martin,V. Dhandapani,D. Triyoso,H.-H. Tseng,Philip J. Tobin,David C. Gilmer,Christopher C. Hobbs,William J. Taylor,J. M. Grant,Rama I. Hegde,J. Mogab,C. Thomas,P. Abramowitz,M. Moosa,J. Conner,Jack Jiang,V. Arunachalarn,Michael A. Sadd,Bich-Yen Nguyen,Bruce E. White +26 more
TL;DR: In this paper, a dual-metal gate CMOS integration on HfO/sub 2/ gate dielectric using TiN (PMOS) and TaSiN (NMOS) gate electrodes was reported.
Proceedings Article
Metal gate MOSFETs with HfO2 gate dielectric
S. Samavedam,H.-H. Tseng,Philip J. Tobin,J. Mogab,S. Dakshina-Murthy,L. B. La,J. A. Smith,J. Schaeffer,M. Zavala,Ryan Martin,Bich-Yen Nguyen,L. Hebert,O. Adetutu,V. Dhandapani,T-Y. Luo,R. Garcia,P. Abramowitz,M. Moosa,David Gilmer,Chris Hobbs,W. Taylor,John M. Grant,Rama I. Hegde,S. Bagchi,E. Luckowski,V. Arunachalam,M. Azrak +26 more
TL;DR: In this paper, the first time electrical characterization of HfO 2 p- and n-MOSFETs with CVD TiN and PVD TaSiN gates respectively fabricated using conventional CMOS integration was reported.
Proceedings ArticleDOI
Metal gate MOSFETs with HfO/sub 2/ gate dielectric
S. Samavedam,H.-H. Tseng,Philip J. Tobin,J. Mogab,S. Dakshina-Murthy,L. B. La,J. A. Smith,J. Schaeffer,M. Zavala,Ryan Martin,Bich-Yen Nguyen,L. Hebert,O. Adetutu,V. Dhandapani,T. Y. Luo,R. Garcia,P. Abramowitz,M. Moosa,David Gilmer,Chris Hobbs,W. Taylor,John M. Grant,Rama I. Hegde,S. Bagchi,E. Luckowski,V. Arunachalam,M. Azrak +26 more
TL;DR: In this article, the first time electrical characterization of HfO/sub 2/ p- and n-MOSFETs with CVD TiN and PVD TaSiN gates respectively fabricated using conventional CMOS integration was reported.
Proceedings ArticleDOI
Integration of UTR processes into MPU IC manufacturing flows
Jonathan L. Cobb,S. Dakshina-Murthy,Colita Parker,E. Luckowski,Arturo M. Martinez,Richard D. Peters,Wei Wu,Scott Daniel Hector +7 more
TL;DR: In this paper, gates have been patterned with 140-nm thick resist films with 10-15 defects per wafer, none of which are specific to the UTR process, and similar UTR gates were also patterned over 80-nm steps with no defects associated with the topography.