Open AccessDOI
Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach
Martin Schoeberl,Pascal Schleuniger,Wolfgang Puffitsch,Florian Brandner,Christian W. Probst,Sven Karlsson,Tommy Thorn +6 more
- Vol. 18, pp 11-21
Reads0
Chats0
TLDR
This paper presents Patmos, a processor optimized for low WCET bounds rather than high average case performance, a dual- issue, statically scheduled RISC processor that relies on a customized compiler.Abstract:
Current processors are optimized for average case performance, often leading to a high worst-case execution time (WCET). Many architectural features that increase the average case performance are hard to be modeled for the WCET analysis. In this paper we present Patmos, a processor optimized for low WCET bounds rather than high average case performance. Patmos is a dual- issue, statically scheduled RISC processor. The instruction cache is organized as a method cache and the data cache is organized as a split cache in order to simplify the cache WCET analysis. To fill the dual-issue pipeline with enough useful instructions, Patmos relies on a customized compiler. The compiler also plays a central role in optimizing the application for the WCET instead of average case performance.read more
Citations
More filters
Journal ArticleDOI
T-crest
Martin Schoeberl,Sahar Abbaspour,Benny Akesson,Neil Audsley,Raffaele Capasso,Jamie Garside,Kees Goossens,Sven Goossens,Scott Hansen,Reinhold Heckmann,Stefan Hepp,Benedikt Huber,Alexander Jordan,Evangelia Kasapaki,Jens Knoop,Yonghui Li,Daniel Prokesch,Wolfgang Puffitsch,Peter Puschner,Andre Rocha,Claudio Silva,Jens Sparsø,Alessandro Tocchi +22 more
TL;DR: Within the T-CREST project the authors propose novel solutions for time-predictable multi-core architectures that are optimized for the WCET instead of the average-case execution time.
Predictable Flight Management System Implementation on a Multicore Processor
Guy Durrieu,Madeleine Faugere,Sylvain Girbal,Daniel Gracia Perez,Claire Pagetti,Wolfgang Puffitsch +5 more
TL;DR: This paper presents an approach for hosting a representative avionic function on a distributed-memory mul-ticore COTS architecture developed in collaboration by Thales and ONERA in order to improve the performance of the function while enforcing its predictability.
Proceedings ArticleDOI
On the Sustainability of the Extreme Value Theory for WCET Estimation
TL;DR: In this article, the authors make more formal extreme value theory applicability to safe worst-case execution time estimations, and conclude about safety of the probabilistic worstcase execution estimations from the Extreme Value theory, and execution time measurements.
Journal ArticleDOI
Patmos: a time-predictable microprocessor
TL;DR: This paper designs and optimize a processor, called Patmos, for low WCET bounds rather than for high average-case performance, a way out of this dilemma: a processor designed for real-time systems.
Proceedings ArticleDOI
The T-CREST approach of compiler and WCET-analysis integration
TL;DR: It is shown that a predictable architecture and the tight and seamless integration of compilation and WCET analysis is beneficial to achieve the initial two goals of good worst-case performance and the availability of high-quality bounds on the WCET of computation tasks.
References
More filters
Proceedings ArticleDOI
LLVM: a compilation framework for lifelong program analysis & transformation
Chris Lattner,Vikram Adve +1 more
TL;DR: The design of the LLVM representation and compiler framework is evaluated in three ways: the size and effectiveness of the representation, including the type information it provides; compiler performance for several interprocedural problems; and illustrative examples of the benefits LLVM provides for several challenging compiler problems.
Book
Embedded Computing: A VLIW Approach to Architecture, Compilers and Tools
TL;DR: A new age of embedded computing design is described, in which the processor is central, making the approach radically distinct from contemporary practices of embedded systems design, and why it is essential to take a computing-centric and system-design approach to the traditional elements of nonprogrammable components, peripherals, interconnects and buses.
Journal ArticleDOI
The influence of processor architecture on the design and the results of WCET tools
TL;DR: The designs of WCET tools for a series of increasingly complex processors, including SuperSPARC, Motorola ColdFire 5307, and Motorola PowerPC 755, are described, and some advice is given as to the predictability of processor architectures.
Journal ArticleDOI
Memory Hierarchies, Pipelines, and Buses for Future Architectures in Time-Critical Embedded Systems
Reinhard Wilhelm,Daniel Grund,Jan Reineke,Marc Schlickling,Markus Pister,Christian Ferdinand +5 more
TL;DR: The architectural influence on static timing analysis is described and recommendations as to profitable and unacceptable architectural features are given and results show that measurement-based methods still used in industry are not useful for quite commonly used complex processors.
Proceedings ArticleDOI
The case for the precision timed (PRET) machine
Stephen A. Edwards,Edward A. Lee +1 more
TL;DR: It is time for a new era of processors whose temporal behavior is as easily controlled as their logical function, and these machines are called precision timed (PRET) machines.
Related Papers (5)
T-crest
Martin Schoeberl,Sahar Abbaspour,Benny Akesson,Neil Audsley,Raffaele Capasso,Jamie Garside,Kees Goossens,Sven Goossens,Scott Hansen,Reinhold Heckmann,Stefan Hepp,Benedikt Huber,Alexander Jordan,Evangelia Kasapaki,Jens Knoop,Yonghui Li,Daniel Prokesch,Wolfgang Puffitsch,Peter Puschner,Andre Rocha,Claudio Silva,Jens Sparsø,Alessandro Tocchi +22 more