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Xi Sung Loo
Researcher at Massachusetts Institute of Technology
Publications - 23
Citations - 93
Xi Sung Loo is an academic researcher from Massachusetts Institute of Technology. The author has contributed to research in topics: CMOS & Noise (electronics). The author has an hindex of 6, co-authored 23 publications receiving 79 citations. Previous affiliations of Xi Sung Loo include GlobalFoundries & Nanyang Technological University.
Papers
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Journal ArticleDOI
THRU-Based Cascade De-embedding Technique for On-Wafer Characterization of RF CMOS Devices
TL;DR: An accurate two-port cascade-based de-embedding technique is presented for characterization of RF devices that outperforms the existing de- embedding techniques by showing distinct capability of accounting for both series contact resistance and distributed effects of interconnects.
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A New Millimeter-Wave Fixture Deembedding Method Based on Generalized Cascade Network Model
Xi Sung Loo,Kiat Seng Yeo,Kok Wai Johnny Chew,L. H. K. Chan,S.N. Ong,Manh-Anh Do,Chirn Chye Boon +6 more
TL;DR: In this paper, a universal cascade-based deembedding technique was presented for on-wafer characterization of the RF CMOS device, which is based on unique combinations of two THRU structures that enable efficient de-embedding of fixture parasitics without any inaccurate lumped approximation or requirement.
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MOSFET Drain Current Noise Modeling With Effective Gate Overdrive and Junction Noise
TL;DR: In this paper, a drain current noise model that includes the channel thermal noise and the shot noise generated at the source-bulk junction and the drain-binning junction is presented.
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A Hybrid Pad-Line-Finger De-Embedding Technique for Broadband Modeling of CMOS Transistor
TL;DR: In this article, a hybrid cascade series-parallel based de-embedding technique is presented for accurate broadband modeling of CMOS transistor, which relies on a unique set of PAD-LINE test structures to extract line parasitics without any inaccurate lumped assumptions.
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An Accurate Two-Port De-Embedding Technique for RF/Millimeter-Wave Noise Characterization and Modeling of Deep Submicrometer Transistors
TL;DR: In this paper, an accurate and simple noise de-embedding technique is proposed for high-frequency noise characterization of transistors, which is demonstrated on 0.13-μm CMOS devices for up to 80 GHz.