The short-circuit (SC) failure mechanism of double-trench silicon carbide (SiC) power metal–oxide–semiconductor field-effect transistors (MOSFETs) is comprehensively studied and analyzed. Unlike traditional planar-gate devices which die from thermal runaway, the double-trench ones exhibit a different SC failure phenomenon. After enduring an ultimate SC stress cycle, the gate of the double-trench device breaks down while the conducting and blocking characteristics of the body diode remain stable. During the SC process, a substantial negative gate current from the semiconductor side to the poly gate side is observed. Silvaco TCAD simulations demonstrate that ultrahigh current density and impact ionization appear at the gate trench corners simultaneously, driving the generated hot holes through the oxide, forming the negative gate current. The sustained action of this gate current component on the oxide finally results in the failure. Moreover, the influence that bias voltages have on the SC endurance capability of the device is analyzed. In general, the higher the ${V}_{\text {ds}}$ and ${V}_{\text {gs}}$ are the shorter the SC endurance time will be. It is also found that the double-trench device fails with a higher junction temperature when stressed under a lower ${V}_{\text {ds}}$ condition, implying that the temperature rarely affects the failure, proving the correctness of the proposed SC failure mechanism.

Understanding Short-Circuit Failure Mechanism of Double-Trench SiC Power MOSFETs

In this article, the static, dynamic, and short-circuit properties of 1.2-kV commercial 4H-SiC planar and trench gate metal–oxide–semiconductor field-effect transistors (MOSFETs) are compared and analyzed in a wide temperature range from 90 to 493 K. The temperature-dependent specific ON-resistance ( ${R}_{\text {sp}- \mathrm{\scriptscriptstyle ON}}$ ) and threshold voltage ( ${V}_{\text {th}}$ ) are analyzed in relation to the density of the interface state. The turn-on rise and turn-off fall times ( ${T}_{r}$ and ${T}_{f}$ ) and the corresponding energy loss ( ${E}_{r}$ and ${E}_{f}$ ) are extracted from a double-pulse test from cryogenic to high temperature and analyzed. The short-circuit capability of the two structures is studied at low temperature for the first time. The comprehensive comparison and analysis of the planar and trench gate MOSFET versus temperature in this work show the importance to study applications with SiC MOSFETs in a wide temperature range, especially for the cryogenic temperatures.

Comprehensive Characterization of the 4H-SiC Planar and Trench Gate MOSFETs From Cryogenic to High Temperature

A novel planar gate SiC MOSFET embedding low barrier diode (LBD-MOSFET) with improved third quadrant and switching performance is proposed and characterized in this letter. The LBD-MOSFET not only exhibits about 3 times lower diode turn on voltage than the body diode, but also successfully eliminates bipolar degradation phenomena. A low potential barrier for electrons transporting from JFET region to N+ source region is formed in LBD-MOSFET owing to the existence of the depletion charge in LBD base region. Meanwhile, the gate-to-drain charge ( ${Q}_{\text {gd}}){}$ and gate-to-drain capacitance ( ${C}_{\text {gd}}){}$ of LBD-MOSFET are significantly reduced by about $21\times $ and $15\times $ in comparison with the conventional MOSFET (C-MOSFET), due to the reduction of the overlapping area of the gate and drift region. Therefore, the obtained high frequency figures of merit (HF-FOM $1= {R}_{\text {on,sp}}\times {Q}_{\text {gd}}$ and HF-FOM $2= {R}_{\text {on,sp}}\times {C}_{\text {gd}}$ ) for the LBD-MOSFET are improved by about 13 times and 9 times compared with C-MOSFET. Furthermore, a compact potential barrier analytical model based on Poisson’s Law is developed to understand the origin of low potential barrier diode in SiC LBD-MOSFET. The overall enhanced performances suggest SiC LBD-MOSFET is an excellent choice for high frequency power electronic applications.

A Novel SiC MOSFET Embedding Low Barrier Diode With Enhanced Third Quadrant and Switching Performance

A novel SiC double-trench MOSFET (DT-MOS) with embedded MOS-channel diode is proposed and investigated via TCAD simulations in this article. The parasitic body diode is free from activation when the device serves as a freewheeling diode, thus completely eliminating the bipolar degradation. Moreover, the proposed MOSFET features superior dynamic characteristics. The gate charge ( ${Q}_{\text {G}}$ ) and gate-to-drain charge ( ${Q}_{\text {GD}}$ ) are reduced by a factor of ~1.8 and ~3.9, respectively, when compared to the conventional state-of-the-art SiC DT-MOS. Combined with the slightly increased ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}}$ ), remarkably improved figures of merit ( ${R}_{ \mathrm{\scriptscriptstyle ON}} \times {Q}_{\text {G}}$ and ${R}_{ \mathrm{\scriptscriptstyle ON}}\times {Q}_{\text {GD}}$ are reduced by a factor of ~1.7 and ~3.7, respectively) are obtained in the proposed structure. When working as a switching device under 200 kHz, the proposed MOSFET could save nearly 64% of the total power losses, making it more conductive to high-frequency applications. In addition, the influence of parameters variation on the device performance is discussed as well.

SiC Double-Trench MOSFETs With Embedded MOS-Channel Diode

SiC metal–oxide–semiconductor field-effect transistor (MOSFET) has a fast switching speed and high slew rate. However, its ultrashort switching time approximates the rise time and propagation delay of the measurement instruments, which results in an inaccurate assessment of the switching loss and challenges the thermal design of the power converter. In this article, aiming to reveal the principles of accurate measurement for the switching behavior of SiC MOSFET, insightful models are proposed for baseline probes and transient trajectories to characterize the measurement error of the switching losses. By using the Gaussian function, the mathematical models for the rise time, bandwidth, and propagation delay of the measurement instruments are achieved, which is also confirmed by the surveyed specifications of commercial probes. Concerning the accurate measurement, the turn-on and turn-off losses of the SiC MOSFET influenced by the rise time and propagation delay of probes are comprehensively modeled and characterized. With respect to different current probes, voltage probes, and gate driver resistances, extensive experiments are demonstrated to confirm the validity of the proposed models. The experimental findings are in line with the conducted predictions of the proposed models. It is found that, due to the very fast switching transients of the SiC MOSFET, the limited bandwidth and inevitable propagation delay of measurement instrument may result in a prominent error of the switching loss and impede the widespread implementation of the SiC MOSFET.

Inaccurate Switching Loss Measurement of SiC MOSFET Caused by Probes: Modelization, Characterization, and Validation

In this paper, an improved 4H-SiC U-shaped trench-gate metal–oxide–semiconductor field-effect transistors (UMOSFETs) structure with low ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}}$ ) and switching energy loss is proposed. The novel structure features an added n-type region, which reduces ON-resistance of the device significantly while maintaining the breakdown voltage ( ${V}_{\textsf {BR}}$ ). In addition, the gate of the improved structure is designed as a p-n junction to reduce the switching energy loss. Simulations by Sentaurus TCAD are carried out to reveal the working mechanism of this improved structure. For the static performance, the ON-resistance and the figure of merit (FOM $= {V}_{\textsf {BR}}^{\textsf {2}}/{R}_{ \mathrm{\scriptscriptstyle ON}}$ ) of the optimized structure are improved by 40% and 44%, respectively, as compared to a conventional trench MOSFET without the added n-type region and modified gate. For the dynamic performance, the turn-on time ( ${T}_{ \mathrm{\scriptscriptstyle ON}}$ ) and turn-off time ( ${T}_{ \mathrm{\scriptscriptstyle OFF}}$ ) of the proposed structure are both shorter than that of the conventional structure, bringing a 43% and 30% reduction in turn-on energy loss and total switching energy loss ( ${E}_{\mathbf {SW}}$ ).

An Improved 4H-SiC Trench-Gate MOSFET With Low ON-Resistance and Switching Loss

This paper presents an optimized normally off GaN-based metal–insulator–semiconductor field-effect transistor (MISFET) with an electrode-connected p-i-n diode inserted in the buffer layer, i.e., EC-PIN MISFET, and in which the substrate is removed for the suppression of the vertical leakage current. We provide the simulation results of the proposed MISFET. The EC-PIN MISFET with $\text{L}_{\textsf {gd}}= \textsf {6} ~\mu \text{m}$ presents an excellent breakdown voltage of 1400 V, which attributes to the improvement of electric field distribution in the gate–drain region and the suppression of leakage current by EC-PIN. In addition, the specific on resistance of 0.64 $\text{m}\Omega \cdot \textsf {cm}^{\textsf {2}}$ and Baliga’s figure of merit of 3.08 GW $\,\cdot \,\textsf {cm}^{-\textsf {2}}$ are achieved in the optimized EC-PIN MISFET, indicating a good tradeoff between the specific on resistance and breakdown voltage.

TCAD Simulation of Breakdown-Enhanced AlGaN-/GaN-Based MISFET With Electrode-Connected p-i-n Diode in Buffer Layer

In this article, we investigate a new hardened GaN MISFET with an integrated Schottky contact (SC-MISFET). The new device architecture significantly improves the single-event burnout (SEB) characteristics. Compared to the field plate conventional GaN MISFET (FPC-MISFET), the Schottky metal can extract a larger number of holes, which are generated by heavy-ion irradiation. In addition, the number of carriers involved in the impact ionization process is substantially reduced. These features enable the new hardened structure to achieve a better overall SEB characteristic. After heavy-ion irradiation, the SEB threshold voltages of devices with conventional and hardened structures are 520 and 710 V, respectively.

Simulation Study of Single-Event Burnout in GaN MISFET With Schottky Element

Research of single-event burnout and hardened GaN MISFET with embedded PN junction

This paper proposes a new breakdown-enhanced GaN MISFET with the architecture of double channel and P-buried layer, i.e. DCP-MISFET. The lower barrier and lower channel are connected with the drain, the lower two dimensional electron gas can improve the device electric field distribution between gate and drain, achieving an enhanced breakdown voltage (BV). At the same time, the P buried layer below the gate field plate can reduce the peak electric field around the gate field plate. The proposed simulated device with LGD=15 μm presents an excellent breakdown voltage of 2373 V. In addition, the ON-resistance (RON) of 15.07 Ω•mm and Baliga's figure of merit of 3.736 GW•cm-2 are achieved in the optimized DCP-MISFET. Compared with breakdown voltage 1547 V of the optimized field plate conventional GaN MISFET (FPC-MSIFET), the proposed device increases the breakdown voltage by 53.39% and the Baliga's figure of merit is enhanced by 133.89%.

https://iopscience.iop.org/article/10.1088/1361-6641/ab81b3/pdf

Xin-Xing Fei

Papers

An Improved 4H-SiC Trench-Gate MOSFET With Low ON-Resistance and Switching Loss

TCAD Simulation of Breakdown-Enhanced AlGaN-/GaN-Based MISFET With Electrode-Connected p-i-n Diode in Buffer Layer

Simulation Study of Single-Event Burnout in GaN MISFET With Schottky Element

Research of single-event burnout and hardened GaN MISFET with embedded PN junction

TCAD simulation of a breakdown-enhanced double channel GaN metal–insulator–semiconductor field-effect transistor with a P-buried layer