Journal ArticleDOI
Subthreshold current reduction for decoded-driver by self-reverse biasing (DRAMs)
Takayuki Kawahara,Masashi Horiguchi,Yoshiki Kawajiri,Goro Kitsukawa,Tokuo Kure,Mayu Aoki +5 more
- Vol. 28, Iss: 11, pp 1136-1144
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TLDR
In this paper, the authors presented an analytical expression for sub-threshold current reduction in a decoded-driver by self-reverse biasing, which is inherently required for low-voltage, low-power, high-speed DRAM's for portable equipment.Abstract:Â
Analytical expressions are presented for subthreshold current reduction in a decoded-driver by self-reverse biasing, which is inherently required for low-voltage, low-power, high-speed DRAM's for portable equipment. The scheme involves inserting a switching MOS transistor between the driver circuits and its power supply line. The subthreshold current of the decoded-driver is reduced to the order of 10/sup -3/ in the practical temperature range (250-350 K) with 254 mV of self-reverse biasing voltage, while the delay time is only 3% more than in conventional schemes. The transition time of 1 ms from the operating state to the low subthreshold current state is sufficient to reduce the subthreshold current. The rapid recovery time of 1 ns from the low subthreshold current state does not interrupt the start of normal operation. The subthreshold current reduction was confirmed experimentally using a test chip fabricated with 0.25- mu m technology. >read more
Citations
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Journal ArticleDOI
1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS
TL;DR: In this article, a multithreshold-voltage CMOS (MTCMOS) based low-power digital circuit with 0.1-V power supply high-speed low power digital circuit technology was proposed, which has brought about logic gate characteristics of a 1.7ns propagation delay time and 0.3/spl mu/W/MHz/gate power dissipation with a standard load.
Journal ArticleDOI
Dual-threshold voltage techniques for low-power digital circuits
J.T. Kao,Anantha P. Chandrakasan +1 more
TL;DR: In this article, the authors present several dual-threshold voltage techniques for reducing standby power dissipation while still maintaining high performance in static and dynamic combinational logic blocks MTCMOS sleep transistor sizing issues are addressed, and a hierarchical sizing methodology based on mutual exclusive discharge patterns is presented.
Proceedings ArticleDOI
Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks
TL;DR: Results on a large number of benchmarks indicate that proper input selection can reduce the standby leakage power by more than 50% for some circuits.
Journal ArticleDOI
Spin-transfer torque RAM technology: Review and prospect
TL;DR: This paper reviews the development of MTJ device technology and formulates considerations regarding its memory application, including SPRAM memory cell structure and operation, write voltage limitation, and thermal stability.
Proceedings ArticleDOI
Subthreshold leakage modeling and reduction techniques
TL;DR: In this paper, an overview of current research to control leakage currents, with an emphasis on areas where CAD improvements will be needed, is given, and techniques to model sub-reshold leakage currents at the device, circuit, and system levels.
References
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Performance and hot-carrier effects of small CRYO-CMOS devices
TL;DR: In this article, the performance characteristics of submicrometer CMOS devices operating at low/cryogenic temperatures (CRYO-CMOS) are determined, in relation to the velocity saturation, source-drain resistances, mobility behavior, carrier freeze-out effects, hot-carrier effects, and circuit performance.
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A 1.5 V DRAM for battery-based applications
TL;DR: In this article, a 3.4-m/sup 2/data-line shielded stacked capacitor (STC) cell is proposed to enhance signal-to-noise ratio (SNR) in memory cell array.
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