This paper introduces the first comprehensive and accurate compact resistance-inductance-capacitance-conductance (RLCG ) model for through-silicon vias (TSVs) in 3-D ICs valid from low- to high-frequency regimes, with consideration of the MOS effect in silicon, the alternating-current (ac) conduction in silicon, the skin effect in TSV metal, and the eddy currents in the silicon substrate. The model is verified against electrostatic measurements as well as a commercial full-wave electromagnetic simulation tool and subsequently employed for various performance (delay) analyses. The compact model is also applicable to TSVs made of carbon nanotube (CNT) bundles, once a slight modification (making the effective conductivity complex) is made. Various geometries (as per the International Technology Roadmap for Semiconductors) and prospective materials (Cu, W, and single-walled/multiwalled CNTs) are evaluated, and a comparative performance analysis is presented. It is shown that CNT-bundle-based TSVs can offer smaller or comparable high-frequency resistance than those of other materials due to the reduced skin effect in CNT bundle structures. On the other hand, the performance (delay) analysis indicates that the performance differences among different TSV materials are rather small. However, it is shown that CNTs provide an improved heat dissipation path due to their much higher thermal conductivity. In addition, the improved mechanical robustness and thermal stability of CNTs also favor their selection as TSV materials in emerging 3-D ICs.

Compact AC Modeling and Performance Analysis of Through-Silicon Vias in 3-D ICs

Interconnecting integrated circuits (ICs) and 3-D-ICs to the system board (printed circuit board) are currently achieved using organic or silicon-based interposers. Organic interposers face several challenges in packaging 2-D and 3-D-ICs beyond the 32-nm node, primarily due to their poor dimensional stability and coefficient of thermal expansion (CTE) mismatch to silicon. Silicon interposers made with back-end of line wafer processes can achieve the required wiring and I/O density, but their high-cost limit them to high-performance applications. Glass is proposed as a superior alternative to organic and silicon-based interposers for packaging of future ICs and 3-D-ICs with highest I/Os at lowest cost. This paper presents for the first time a novel thin and large panel glass interposer capable of scaling to 700 mm and larger panels with potential for significant cost reduction over interposers made on 200-mm or 300-mm wafers. The formation of small through vias at high speed has been the biggest technical barrier for the adoption of glass as an interposer and system substrate; and this paper describes pioneering research in via-formation in thin glass substrates, using a novel “polymer-on-glass” approach. Electrical modeling and design of through package vias (TPVs) in glass is discussed in detail, and the feasibility of 50-μm pitch TPVs in 180-μm thin glass substrates has been demonstrated. The excellent surface finish and low CTE of glass leads to increased I/O density, and increased functionality per unit area leading to system miniaturization.

Low-Cost Thin Glass Interposers as a Superior Alternative to Silicon and Organic Interposers for Packaging of 3-D ICs

The ever-increasing demands of digital computing and wireless communication have been driving the semiconductor technology to change with each passing day. Modern electronic systems integrate more complex components and devices, which results in a very complex electromagnetic (EM) field environment. EM compatibility has become one of the major issues in ICs redesign, mainly due to the lack of efficient and accurate simulation tools and expertise on noise reduction and immunity improvement. This paper reviews the state of the arts of IC, electronic package, and printed circuit board simulation and modeling technologies. It summarizes the modeling technologies for both available structures [multilayered power-ground planes and macromodeling of interconnect (INC)] and novel structures (nano-INCs and 3-D ICs based on through-silicon via technology). It also illustrates the trends of simulation and modeling technologies in EM compatibility, signal integrity, and power integrity.

Progress Review of Electromagnetic Compatibility Analysis Technologies for Packages, Printed Circuit Boards, and Novel Interconnects

3D integration consists of 3D IC packaging, 3D IC integration, and 3D Si integration. They are different and in general the TSV (through-silicon via) separates 3D IC packaging from 3D IC/Si integrations since the latter two use TSV but 3D IC packaging does not. TSV (with a new concept that every chip or interposer could have two surfaces with circuits) is the heart of 3D IC/Si integrations and is the focus of this investigation. The origin of 3D integration is presented. Also, the evolution, challenges, and outlook of 3D IC/Si integrations are discussed as well as their road maps are presented. Finally, a few generic, low-cost, and thermal-enhanced 3D IC integration system-in-packages (SiPs) with various passive TSV interposers are proposed.

Evolution, challenge, and outlook of TSV, 3D IC integration and 3d silicon integration

Through-silicon vias (TSVs) in low, medium and high resistivity silicon for 3-D chip integration and interposers are modeled and thoroughly characterized from 100 MHz to 130 GHz, considering the slow-wave, dielectric quasi-TEM and skin-effect modes. The frequency ranges of these modes and their transitions are predicted using resistivity-frequency domain charts. The impact of the modes on signal integrity is quantified, and three coaxial TSV configurations are proposed to minimize this impact. Finally, conventional expressions for calculating the per-unit-length circuit parameters of transmission lines are extended and used to analytically capture the frequency dependent behavior of TSVs, considering the impact of the mixed dielectric (silicon dioxide-silicon-silicon dioxide) around the TSVs. Excellent correlation is obtained between the analytical calculations using the extended expressions and electromagnetic field simulations up to 130 GHz. These extended expressions can be implemented directly in electronic design automation tools to facilitate performance evaluation of TSVs, prior to system design.

High-Frequency Modeling of TSVs for 3-D Chip Integration and Silicon Interposers Considering Skin-Effect, Dielectric Quasi-TEM and Slow-Wave Modes

This paper presents analytical modeling and 3D full-wave electromagnetic (EM) simulation of the bias voltage dependent semiconductor (MOS) capacitance of a Through Silicon Via (TSV). An accurate electrical model of the TSV is proposed by considering the semiconductor effects. The high-frequency electrical performance of TSVs and Through-Package Vias (TPVs) are compared by means of 3D EM simulations. A parametric study is performed on TSV capacitance and design guidelines are presented for signal and power TSVs.

Electrical modeling of Through Silicon and Package Vias

Interposer technology has evolved from ceramic to organic materials and most recently to silicon. Organic substrates exhibit poor dimensional stability, thus requiring large capture pads which make them unsuitable for very high I/Os with fine pitch interconnections. Therefore, there has been a trend to develop silicon interposers. Silicon interposers however, suffer in two ways; 1) they are expensive to process due to the need for electrical insulation around via walls, and 2) they are limited in size by the silicon wafer from which they originate. In this paper, glass is proposed as a superior alternative interposer technology to address the limitations of both silicon and organic interposers. The inherent electrical properties of glass, together with large area panel size availability, make it superior compared to organic and silicon-based interposers. Glass however, is not without its challenges. It suffers in two ways: 1) formation of vias at low cost, and 2) its lower thermal conductivity compared to silicon. This research explores glass as an interposer material, and addresses the above key challenges in through package via (TPV) formation and subsequent low cost and large area metallization to achieve very high I/Os at fine pitch.

Through-package-via formation and metallization of glass interposers

This paper proposes an efficient method to model through-silicon via (TSV) interconnections, an essential building block for the realization of silicon-based 3-D systems. The proposed method results in equivalent network parameters that include the combined effect of conductor, insulator, and silicon substrate. Although the modeling method is based on solving Maxwell's equation in integral form, the method uses a small number of global modal basis functions and can be much faster than discretization-based integral-equation methods. Through comparison with 3-D full-wave simulations, this paper validates the accuracy and the efficiency of the proposed modeling method.

Electromagnetic Modeling of Through-Silicon Via (TSV) Interconnections Using Cylindrical Modal Basis Functions

3-D integration of microelectronic systems reduces the interconnect length, wiring delay, and system size, while enhancing functionality by heterogeneous integration. Through silicon via (TSV) is a key building block for high-performance 3-D systems. This paper presents an accurate electrical modeling of TSVs considering metal-oxide-semiconductor (MOS) capacitance effects. The model is correlated with measurement results for validation. Parametric analysis of TSV capacitance is performed on several physical and material parameters. Design guidelines are proposed for TSVs used in signal and power distribution networks as well as for TSVs as variable capacitors. A 3-D power distribution network is simulated to show the effect and importance of the voltage-dependent TSV MOS capacitance.

Tapobrata Bandyopadhyay

Papers

Low-Cost Thin Glass Interposers as a Superior Alternative to Silicon and Organic Interposers for Packaging of 3-D ICs

Electrical modeling of Through Silicon and Package Vias

Through-package-via formation and metallization of glass interposers

Electromagnetic Modeling of Through-Silicon Via (TSV) Interconnections Using Cylindrical Modal Basis Functions

Rigorous Electrical Modeling of Through Silicon Vias (TSVs) With MOS Capacitance Effects