Showing papers presented at "Asia Symposium on Quality Electronic Design in 2011"

A new architecture for T flip flop using quantum-dot cellular automata

Abstract: QCA is a novel technology which provides implementation of digital circuits in nanoscale. QCA circuits work in higher speed, smaller size and less power consumption compared to conventional CMOS circuits. In this paper, a new design for T flip flop (T-FF), by using of special feature of QCA circuits capabilities, is proposed. This T-FF has additional inputs that can be used better in sequential circuits as memory elements. These inputs can reset and preset T-FF and no more cells needed to add them to the designed circuit. Proposed T-FF is simulated using the QCADesigner and simulation results prove its validity.

Effect of heater geometry on the high temperature distribution on a MEMS micro-hotplate

Abstract: Temperature uniformity on a micro-hotplate is important for gas sensor sensitivity, linearity, and resolution. There are several ways to create a uniform temperature distribution on a micro-hotplate. In this paper, the modification of microheater geometry is the method used. Four different heater geometries are simulated using ConvetorWare software to determine which geometry can give the most uniform temperature distribution. The simulations show that the heater geometry which combines parallel and meander shapes results in the most uniform heat distribution. The electrical potential and current distributions of the four different micro-heater geometries are also evaluated.

Application-specific selection of 6T SRAM cells offering superior performance and quality with a triple-threshold-voltage CMOS technology

Abstract: Conventional six-transistor (6T) memory cell has an intrinsic data stability problem due to directly-accessed storage nodes during a read operation. The data stability issue becomes more severe with increasing variability and decreasing supply voltage in scaled CMOS technologies. Conventional techniques to enhance the data stability of 6T memory cells tend to sacrifice other important figures of merit, such as memory integration density and write ability. 6T SRAM circuits with higher data stability are presented in this paper. An electrical performance metric is evaluated to compare various memory design options targeting different applications. The overall electrical quality is enhanced without increasing the area with a multi-threshold-voltage CMOS technology. A high-threshold-voltage 6T memory cell is recommended for portable devices where lower energy consumption and longer battery lifetime are critically important. Alternatively, a triple-threshold-voltage 6T SRAM cell is recommended for robust memory operation in applications with aggressive speed requirement.

An approach to code compression for CGRA

Abstract: CGRA has been considered to be an attractive architecture for accelerating data-intensive applications due to the performance and flexibility that it can provide. However, the cache memory that stores the configuration code increases the silicon area significantly, making the architecture less attractive. This paper proposes an approach to saving the cache memory space through code compression for CGRA. It is based on the observation that typical configuration code consists of a repetition of same instruction patterns. Experiments with several applications show that the proposed approach reduces the code size by 56% on average and the required cache area by 26% on average and up to 68.6% when the hardware overhead is taken into account.

Uniform diameter and pitch co-design of 16nm n-type carbon nanotube channel arrays for VLSI

Abstract: Uniform nanotube diameter and nanoarray pitch are essential for low-cost and high-yield manufacturability of billions of carbon nanotube MOSFETs (CN-MOSFETs) with various sizes on a single chip. In this paper, the optimum uniform diameter and pitch of 16nm n-type CN-MOSFETs are determined with two different substrate bias voltages for a wide range of transistor sizes. A new quality metric is evaluated to identify the optimum device profiles suitable for very large scale integration.

Analysis, modeling and optimization of transmission gate delay

Abstract: Due to relatively constant and low resistive path between input and output, Transmission gate (TG) logic offers less delay compared to other logic styles without threshold drop while keeping low transistor count. Apart from transition time, the load impedances and initial conditions on internal node capacitances, the critical delay of TG logic depends on chain-length (n) of the circuit and shows quadratic dependency on chain-length. This necessitates buffer insertion at depth 3 or 4 for chain of transmission gate in the current analysis methodology. In this paper, the dependency on two more factors such as fan-out and input-pattern are discussed. We show that the delay is dynamic and exponential depending on input-pattern and fan-out respectively. As a consequence, the insertion of buffer at proper depth is necessary for different fan-out configuration. A restoring mode transmission gate (RMTG) XOR gate is proposed which shows little dependency on fan-out and input patterns thereby eliminate the complexity of buffer insertion. The Spice simulation in 180nM UMC Technology shows that our proposed RMTG XOR is 13.21% and 31.34% faster, 51.63% and 1.72% power efficient compared to the conventional CMOS XOR and TG XOR respectively for a load capacitance of 10 fF. Our proposed model consumes less hardware compared to the conventional CMOS XOR.

Design of lane detection system based on color classification and edge clustering

Abstract: This paper presents a design of system to detect more accurate road lane with image sensor-based color classification and directional edge clustering With treatment of road region and lane as a recognizable color object, the clustering of color cues is processed by an iterative optimization of statistical parameters to each color object These clustered color objects are taken into considerations as initial kernel information for color object detection and recognition In order to improve the limitation of object classification using the color cues, the directional edge cures within the estimated region of interest in the lane boundary (ROI-LB) are clustered and combined The results of color classification and directional edge clustering are optimally integrated to obtain the best detection of road lane The characteristic of the proposed system is to obtain robust result to all real road environments because of using non-parametric approach based only on information of color and edge clustering without a particular mathematical road and lane model The experimental results to the various real road environments and imaging conditions are presented to evaluate the effectiveness of the proposed method

IR drop analysis in single- and multi-wall carbon nanotube power interconnects in sub-nanometer designs

Abstract: This paper presents a detailed analysis of the power supply voltage (IR) drop in sub-nanometer designs for local, semi-global, and global lengths. The IR drop in carbon nanotube (CNT) based power interconnects is analyzed and their effects on the timing delay have been investigated. It is shown that the CNT based power interconnects have significantly less IR-drop in comparison to that of Cu based power interconnects for semi-global and global lengths. The interconnect delay is increased by almost ten times for ten fold increase in interconnect length due to IR-drop in Cu wires, whereas that of MWCNT based wires is only ∼50% for global lengths.

A complete methodology for determining memory BIST optimization under wrappers sharing constraints

Abstract: This paper is about a generic method for designing shared memory BIST systems. In order to be of practical use, such a method should work with whatever memory kinds and BIST components are available for the technology used. It should accept arbitrary sharing rules for grouping memories under a wrapper, and it should take individual values of BIST component area, memory test time and memory testing peak power as parameters. We present such a method that uses genetic algorithms for its optimization phase, together with its industrial implementation, and numerical evidence for the value of the method. It is integrated into STMicroelectronics' BIST definition flow.

A new statistical electromigration analysis methodology that incorporates across-chip temperature variation

Abstract: In this paper, we present a new approach which uses statistical methods to analyze the Electromigration (EM) reliability on a chip This new approach utilizes statistical nature of EM failure distribution to assess overall EM risk of a product Furthermore, we have incorporated within-die temperature variation into the proposed EM analysis to better estimate the EM risk of a product

Influence of the heat sink orientation and fins arrangement on the thermal behavior of high power LED

Abstract: Heat management in Light Emitting Diodes (LED) is necessary to enhance its optical performance and stability. The usage of external heat sink is one of the efficient ways to reduce the thermal effect on the LED packages at low cost.

Multi-stage parallel processing of design element access tasks in FPGA-based logic emulation systems

Abstract: In FPGA based logic emulation systems, effective verification performance not only depends on the frequency at which the design clocks can be advanced, but also on the efficiency of various design element access tasks initiated by associated SW applications like high level testbench, GUI etc. Although existing emulation systems achieve high degree of parallelism in model execution by partitioning the design into multiple FPGAs, the design element access tasks are typically executed sequentially, resulting in suboptimal performance. A multi-stage parallel execution framework for such tasks is presented in this paper. To achieve fine grain parallelism, each task is conceptually decomposed into subtasks for SW processing and HW access, and similar subtasks of multiple tasks are parallelized independently. At SW level, multi-threading of SW processing jobs takes advantage of increasing availability of multi-core processors. Multi-FPGA parallelism is achieved for HW access, to harness independent processing capabilities of a design partition. At a single FPGA level, lazy access mechanism is introduced for parallel processing of multiple HW access tasks, using design specific signal dependency characteristics. The system has been implemented on an industry standard logic emulation system and benchmarks on real designs have shown significant gain in verification performance, while maintaining functional fidelity.

Study on the variation in thermal resistance and junction temperature of GaN based LEDs using thermal transient measurement

Abstract: Proper heat management in solid state lighting (SSL) is vital to enhance its efficiency and reliability. The ease of heat flow through the LED package was described in terms of the thermal resistance, R th . In this study white and green LEDs were used to investigate the variation in junction temperature and junction-to-ambient thermal resistance, R thJA . It was reported that the green LED always shows higher junction temperature and thermal resistance compared to the white LED. This is due to current crowding effect at the p-n junction of the green LED. At 700mA, the R thJA of green LED was increased about 3KW compare with white LED. Furthermore, the die attach quality also influences the temperature rise and thermal resistance of the LED packages. Due to poor die attach, the R thJA rises about 7K/W when compared with good die attach sample.

0.18um low voltage 12-bit successive-approximation-register analog-to-digital converter (SAR ADC)

Abstract: This paper presents a 0.18um process Successive-Approximation Register Analog-to-Digital Converter (SAR ADC) design that can operate at a low voltage of minimum 1.4V across process corners and temperature with the power consumption of less than 100uW. The design comprises three main blocks namely a fully differential latched comparator, binary-weighted capacitors Digital-to-Analog Converter (DAC) and a SAR digital control logic module. The SAR ADC was designed to work at a minimum of 1.4V to cater to the 1.5V AA-battery +/−10% and accepts a maximum clock frequency of 500 kHz. In order to reduce the current consumption, this design uses the capacitors in the DAC as the sample-and-hold (S/H) component, together with a hybrid DAC architecture. The pre-amp used before the comparator has folded-cascode configuration to enable it to work at a low voltage level and differential outputs to account for noise cancellation. This circuit was designed using Silterra C18G 0.18um process.

Display signal interface techniques for mobile applications

Abstract: This paper provides an overview of existing interface technologies and current technical trends for mobile applications. In recent times the display signal interface techniques have rapidly improved providing the desired high-resolution and large-size characteristics. Some of design methodologies for enhancement include working with the signal swing of a display interface whereby as it is decreased the data rate is increased accordingly. For flat panel display (FPD) three interface schemes namely, intermodule interface, intra-panel interface and mobile interface have been important as part of the design space and existed according to the physical location of interface system.

Random work functions induced DC and dynamic characteristic fluctuations in 16-nm high-κ/metal gate CMOS device and digital circuit

Abstract: We study nanosized metal grains induced DC and timing fluctuations in 16 nm high-κ/metal gate (HKMG) MOSFET devices. A localized work function fluctuation (LWKF) on device's DC/AC and CMOS inverter's characteristics is advanced using an experimentally validated 3D device simulation which cannot be well modeled using an averaged WKF (AWKF) method. DC characteristics estimated by the LWKF method are 1.5 and 1.6 times larger than that by the AWKF method for N- and P-MOSFETs, respectively, due to random grain number and position effects. The delay time of high-to-low and low-to-high of the CMOS inverter calculated by the AWKF method are underestimated by 1.29 and 1.19 times, compared with the LWKF method.

Build-in-Self-Test of FPGA for diagnosis of delay fault

Abstract: The recent trend of reconfigurable hardware and convergence of hardware platform in embedded system have enhanced the application of FPGAs. Although the capability and performance of FPGA have advanced, the testing of FPGAs both online and off-line (manufacturer oriented testing) poses a major challenge. Importance of delay testing has grown especially for high-speed circuits. Even presence of small delay fault may cause any critical path to fail. As delay testing, using automatic test equipment is found to be quite expensive; BIST (Built-In-Self-Test) can significantly reduce the cost of delay fault detection without using extra hardware. We have presented a BIST structure to test delay fault of various resources and interconnects of FPGA. The proposed scheme can be implemented for both online as well as off-line testing. We have also proposed a new 3-diagnosable BISTer structure that improves the testing efficiency of our BISTer. The proposed technique can detect the presence of fault, even if all the three units ( TPG, ORA, BUT) in a BIST are faulty. We have simulated our method in Xilinx Vertex-II FPGA, using ISE tool Jbits3.0 API and XHWI (Xilinx Hardware Interface) provided by Xilinx and MATLAB7.0.

Detectability analysis for resistive open faults with dynamic supply voltage scaling awareness

Abstract: Dynamic supply voltage scaling (DVS) is an efficient and practical design technique to reduce power consumption in VLSI devices. Due to the multiple voltage operating environment and the supply voltage dependent behavior of physical faults, obtaining a minimal test set which gives the best fault coverage is challenging. Researchers have showed that testing of resistive opens is best achieved at high supply voltage. However based on our experimental results on ISCAS-85 circuits it is shown that is not always the case for DVS enabled designs. This paper analyzes and identifies different detectability patterns for resistive open faults in such designs. Additionally it discussed the multi-VDD testing and its necessity to achieve 100% fault coverage.

Signal integrity and scalability study of a novel PoP inter-package system

Abstract: A novel enabling technique exploiting interposer approach such as silicon and package interposer [1] in the area of package-on-package (PoP) technology to achieve ultra small form factor packaging solution is presented in this paper. Electrical performance of such interconnect innovation is discussed and pitted against the conventional PoP methods using solder ball connection, as well as the recent developed over-molded interconnection technology. The advantages of the aforementioned silicon and package interposer technology from electrical performance perspective such as signal integrity in terms of impedance matching, noise shielding, electrical return and insertion losses are presented based on 3D passive modeling and simulation data. Device input-output (IO) density and physical scalability as associated with the above inter-package connection systems are also being analyzed and further elaborated. Transient analysis in terms of impulse response and TDR are presented in this paper as well.

NBTI-induced 8-Bit DAC circuit mismatch in System-On-Chip (SoC)

Abstract: This paper focuses on Negative Bias Temperature Instability (NBTI) awareness to the circuit designer for reliable design of the System-On-a-Chip (SoC) analog circuit. The reliability performance of all matched pair such as current source and differential pair circuits, such as Bandgap Reference, is at the mercy of aging differential. Aging simulation (AgingSim) is mandatory to obtain realistic risk evaluation for circuit design reliability qualification. It is applicable to all circuit aging problems covering both analog and digital. Failure rate varies as a function of voltage and temperature. It is shown that PMOS is the reliability-critical device and NBTI is the most critical failure mechanism for analog circuit performance in sub-micrometer CMOS technology. This paper provides a complete reliability simulation analysis of an 8 bit Cathode-Ray-Tube (CRT) Digital-Analog-Converter (DAC) under 90nm process technology and analyze the effect of NBTI using aging simulation tool. A Burn-In experiment was performed to review the reliability sensitivity of the DAC design.

A white LED backlight driving IC with 3-bit dimming controller

Abstract: This paper presents a white LED backlight driving chip with 3-bit dimming controller and duty-variable power MOS which can be modified with the voltage-mode pulse width modulation (PWM). In the proposed chip, a 3-bit digital-to-analog converter (DAC) and a ramp generator are used to provide eight pulses with variable width through a voltage comparator. Thus, a 3-bit dimming controller can be implemented with those duty cycles for white LED backlight driver. In this paper, the proposed chip is designed and implemented with TSMC 0.35 µm 2P4M CMOS process. The simulation results of the switching DC-DC boost converter show that the output voltage, output current, and chip area are 20 V, 20 mA, and 1.45×1.28 mm2, respectively, at the supply voltage of 3.7 V. The output voltage of 20 V can drive five white LEDs because that a white LED works with a driving voltage of 3.5 V and a driving current of 20 mA.

Routing-aware placement technique for intelligent collision avoidance in digital microfluidic biochips

Abstract: The current advancement in microfluidics and microfabrication technology makes it possible to realize true multifunctional lab-on-chip systems that can replace a real life laboratory system with a miniaturized microsystem. The huge advantages of such systems are that they enable fast, easy-to-use, cost-effective detection methods which find major application in the areas of clinical diagnostics, DNA sequencing, drug discovery and other biochemical analyses and applications. As the design of droplet based microfluidic biochips tends to incorporate concurrent execution of multiple bioassays in a single chip, the design complexity as well as system integration issues begin to pose major challenges. A potential CAD problem in this context is the concurrent routing of droplets in DMFBs. This has direct impact on overall reaction time as well as cell usage and pin requirements (specifically in direct-addressing biochips). In this paper we propose a routing-aware placement algorithm for droplets in a digital microfluidic system with a given prescheduled module arrangement. The objective is to enhance the routing process by intelligent collision avoidance, optimized stalling and detour, which finally results in stark improvement in latest arrival time and resource utilization. The proposed algorithm is tested on benchmark suite I for 2-pin droplets and Benchmark suite III for multipin droplets. The results obtained are quite encouraging.

Outlier distribution detection approach to semiconductor wafer fabrication process monitoring

Abstract: It is well known that most of the defect clusters found on the fabricated semiconductor wafers have an assignable cause, which if rectified quickly can improve product quality and lower the production cost. This paper proposes a statistical correlation method that extends an existing Automatic Defect Cluster Analysis System (ADCAS). The method can be implemented in real-time such that the manufacturing cost would not be negatively affected. The proposed system generates a list of equipment having a high likelihood of causing the systematic failure. This technique is fast and easy to implement, and it provides early detection and prevention of failures associated with problematic equipment/process during manufacturing.

Near-threshold 40nm Supply Feedback C-element

Abstract: The growing demand for ultra low power applications has drawn interest in low voltage digital circuits, operating in the near-threshold region. Asynchronous circuits, operating with near-threshold supply voltages, are more attractive than their synchronous counterparts due to higher resilience to PVT variations. This paper presents a novel ultra-low power C-element, which is a basic building block in common asynchronous circuits. The proposed C-element is based on a Supply Feedback concept, implemented in a cross-coupled inverter latch. Utilization of this concept enables functionality under local and global variations down to 0.3V. The cell was designed using a standard low-power 40nm technology. Simulation results show a 5.8X–24X leakage reduction at 300mV as compared to a conventional Weak Feedback C-element operating at its minimal V DD . Monte Carlo simulations prove that the proposed cell remains fully functional under global and local process variations.

Optimization of arsenic and phosphorus Source/Drain implantation for low power NMOS device

Abstract: In low leakage MOS device fabrication, careful pn junction design is critical to control overall device leakage, such as Band-To-Band Tunneling (BTBT) and Gate-Induced Drain Leakage (GIDL) that are always taken into consideration by device designers. Source/Drain implantation also play a very important role in suppressing silicon dislocation effect, which increases implanted species transient-enhanced diffusion (TED) and induces shallow-junction leakage. In this paper, we describe and analyze optimization works on arsenic and phosphorus Source/Drain implantation for 1.5V low power NMOS in a 0.13um technology. Optimized condition of the Source/Drain implantation can suppress dislocation defect which affects 1.5V NMOS off-state leakage current. By implementing the optimized condition, we improved the 1.5V NMOS off-state leakage current by 65.4%, and achieved higher junction breakdown. Furthermore, device characterization gave robust integrated circuit operation speed.

Thermal modeling of three-dimensional integrated circuits considering the thermal removal capability of different TSVs

Abstract: In this paper, a thorough comparison of the heat removal capability of different types of through silicon vias (TSVs) for three-dimensional ICs is presented. It is shown that power TSVs with the associated power delivery network (PDN) has significantly better heat removal capability than the other types of TSVs. An accurate and efficient thermal simulation methodology is then proposed by incorporating an accurate heat removal model of the PTSVs and PDN. Experimental results show that the accuracy of the proposed methodology is close to that of detailed 3-D finite volume based heat solver, while the computational effort is much lower.

A novel integrated amorphous silicon TFT gate driver circuit with optimized design for TFT-LCD display panel manufacturing

Abstract: In this work, we design and optimize a new amorphous silicon gate (ASG) driver circuit for GOP (gate-on-panel) application in medium size LCD. The circuit is composed of sixteen TFTs and one capacitor with distinct pre-charge nodes and dual low voltage levels. The design of distinct pre-charge nodes is conducive to the decrease of the charge time, and the dual low voltage level will stabilize the output waveform in off-duty periods. Biology-inspired global optimization technique is thus advanced to optimize circuit parameter for further improvement of dynamic characteristics. The optimization not only considers output characteristics but the pre-charge node voltage fluctuation, which may lead serious variation to output waveform when the temperature becomes higher. The results of our design including optimization indicate the achieved circuit performance is apparently better than an original design, where the associated sensitivity analysis is examined to assess the variation of optimized specification. The proposed new design is useful for manufacturing.

Comparison of isotropic dry etching process using XeF2 and ANisotropic Wet Etching Process using EDP for microhotplate device

Abstract: This paper discusses the difference between isotropic dry etching process using XeF 2 and anisotropic wet etching process using Ethyl Diamine Pyrocathecol (EDP). The process is a bulk-etch process necessary for obtaining a suspended structure in a microhotplate device. For the dry etching process using XeF2, the pressure of the nitrogen gas is fixed to 0 Torr, while the pressure of XeF 2 is fixed to 2.5Torr. Wet etching process using EDP is conducted in a fume cupboard with 75 ml ethylene diamine, 12 g pyrocathecol, and 10 ml water. Results show that both of these processes are suitable for a microhotplate device. However, there are some differences between the wet and dry etching processes that have to be considered when etching a microhotplate device. The differences in terms of surface condition, time to obtain the suspended structure, and etch rate for each etching process are discussed in detail in this paper.

A 3.1–10.6 GHz frequency tunable ultra wideband LNA

Abstract: This paper presents an ultra-wideband (UWB) low noise amplifier (LNA) which is implemented with TSMC 0.18-µm CMOS process. In the proposed chip, both shunt-series feedback and bandpass filter are used to complete the input matching of the desired ultra broadband chip; and that the power consumption is reduced using the current reused method. Besides, not only the isolation of LNA is improved with a cascade amplifier, but also the output matching is achieved with buffer. Finally, a multiple gated circuit is added to improve the linearity. The simulation results of the proposed UWB LNA shows that the isolation, input return loss, output return loss, power consumption are −83 dB, −12.3 dB, −11.1 dB, and 12.2 mW, respectively; and that the power gain from 11.5 dB to 13.4 dB, gain flatness of 0.245, and noise figure from 3.8 dB to 4.7 dB are obtained at frequency bandwidth from 3.1 GHz to 10.6 GHz. Notify that the simulated P 1dB and IIP 3 are −11.25 dBm and −13.28 dBm, respectively, at frequency of 6 GHz.

Linearization of GaN power amplifier using feedforward and predistortion techniques

Abstract: This paper investigates the feasibility of linearizing GaN power amplifier using the diode-based predistortion and the feed-forward techniques For the diode-based predistortion technique, a new strategy is presented for selecting the breakpoints on a typical linearizer characteristic Using this strategy, a new diode-based curve-fitting predistortion linearizer for GaN power amplifier is developed The proposed linearizer is tested using the two-tone test The experimental results show that a 3 dB improvement in the overall gain of the linearized amplifier is achieved Moreover, for output power levels up to 36 dBm, the linearized power amplifier provides better rejection of the third-order intermodulation Because of the hard nonlinearity of the GaN power amplifier at the high end, this improvement in intermodulation rejection vanishes for output power levels around 41 dBm For the feedforward technique the simulation results show that the 1 dB compression point has been increased from the original 40 dBm for unlinearized amplifier to 4374 dBm for the linearized one