International Test Conference 

About: International Test Conference is an academic conference. The conference publishes majorly in the area(s): Automatic test pattern generation & Fault coverage. Over the lifetime, 4928 publications have been published by the conference receiving 100353 citations.

Model for Delay Faults Based Upon Paths

Abstract: Delay testing of combinational logic in a clocked environment is analyzed. A model based upon paths is introduced for delay faults. Any path with a total delay exceeding the clock interval is called a "path fault." This is a global delay fault model because it is associated with an entire path. The more familiar slow-to-rise or slow-to-fall gate delay fault, on the other hand, is a local fault model. A procedure is described which identifies paths which are tested for path faults by a set of patterns. It does not involve delay simulation. The paths so identified are tested for path faults independent of the delays of any individual gate of the network.

Socrates : A Highly Efficient Automatic Test Pattern Generation System

Abstract: An automatic test pattern generation system, SOCRATES, is presented. SOCRATES includes several novel concepts and techniques that significantly improve and accelerate the automatic test pattern generation process for combinational and scan-based circuits. Based on the FAN algorithm, improved implication, sensitization, and multiple backtrace procedures are described. The application of these techniques leads to a considerable reduction of the number of backtrackings and an earlier recognition of conflicts and redundancies. Several experiments using a set of combinational benchmark circuits demonstrate the efficiency of SOCRATES and its cost-effectiveness, even in a workstation environment. >

Testing embedded-core based system chips

Abstract: Advances in semiconductor process and design technology enable the design of complex system chips. Traditional IC design in which every circuit is designed from scratch and reuse is limited to standard-cell libraries, is more and more replaced by a design style based on embedding large reusable modules, the so-called cores. This core-based design poses a series of new challenges, especially in the domains of manufacturing test and design validation and debug. This paper provides an overview of current industrial practices as well as academic research in these areas. We also discuss industry-wide efforts by VSIA and IEEE P1500 and describe the challenges for future research.

Embedded deterministic test for low cost manufacturing test

Abstract: This paper introduces embedded deterministic test (EDT) technology, which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time. The EDT architecture, the compression algorithm, design flow, experimental results, and silicon implementation are presented.

Test wrapper and test access mechanism co-optimization for system-on-chip

Abstract: Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip (SoC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrapper design problem at a time, i.e., either optimizing the TAMs for a set of pre-designed wrappers, or optimizing the wrapper for a given TAM width. In this paper, we address a more general problem, that of carrying out TAM design and wrapper optimization in conjunction. We present an efficient algorithm to construct wrappers that reduce the testing time for cores. Our wrapper design algorithm improves on earlier approaches by also reducing the TAM width required to achieve these lower testing times. We present new mathematical models for TAM optimization that use the core testing time values calculated by our wrapper design algorithm. We further present a new enumerative method for TAM optimization that reduces execution time significantly when the number of TAMs being designed is small. Experimental results are presented for an academic SoC as well as an industrial SoC.