Showing papers presented at "Workshop On Computer Architecture Education in 2019"

WebRISC-V: a Web-Based Education-Oriented RISC-V Pipeline Simulation Environment

Abstract: WebRISC-V is a web-based server-side RISC-V assembly language Pipelined Datapath simulation environment, which aims at easing students learning and instructors teaching experience. RISC-V is an open-source Instruction Set Architecture (ISA) that is highly flexible, modular, extensible and royalty free. Because of these reasons, there is an exploding interest both in the industry and academia for the RISC-V. Here, we present the main features of this simulator and how it can be used for a simple exercise in the classroom. This web-based simulator permits the execution of RISC-V user-provided source code on a five-stage pipeline, while displaying the data of registers, memory and the internal state of the pipeline elements. One of the main advantages of WebRISC-V is the immediate availability in the web browser, thanks to its implementation as a server-side script in PHP.

Teaching Heterogeneous Computing with System-Level Design Methods

Abstract: We present our work at Columbia University teaching the design and programming of heterogeneous computing architectures with SLD methods. Over the past eight years, we have developed a new course, System-on-Chip Platforms, with the main goal of preparing students to contribute to the new economy of heterogeneous computing and open-source hardware. The course was one of the first nationwide to introduce the use of commercial high-level synthesis tools for the design of application-specific hardware accelerators. We also introduced the idea of structuring the final project as a design-space exploration contest that combines aspects of collaborative engineering and design for reusability.

The BRISC-V Platform: A Practical Teaching Approach for Computer Architecture

Abstract: Computer architecture lies at the intersection of electrical engineering, digital design, compiler design, programming language theory and high-performance computing. It is considered a foundational segment of an electrical and computer engineering education. RISC-V is a new and open ISA that is gaining significant traction in academia. Despite it being used extensively in research, more RISC-V-based tools need to be developed in order for RISC-V to gain greater adoption in computer organization and computer architecture classes. To that end, we present the BRISC-V Platform, a design space exploration tool which offers: (1) a web-based RISC-V simulator, which compiles C and executes assembly within the browser, and (2) a web-based generator of fully-synthesizable, highly-modular and parametrizable hardware systems with support for different types of cores, caches, and network-on-chip topologies. We illustrate how we use these tools in teaching computer organization and computer architecture classes, and describe the structure of these classes.

The Davis In-Order (DINO) CPU: A Teaching-focused RISC-V CPU Design

Abstract: The DINO CPU is an open source teaching-focused RISC-V CPU design available on GitHub (https://github.com/jlpteaching/dinocpu). We have used the DINO CPU in the computer architecture course at UC Davis for two quarters with two separate instructors. In this paper, we present details of the DINO CPU, the tools included with the DINO CPU, and our experiences using the DINO CPU.

PyRTL in Early Undergraduate Research

Abstract: Undergraduate research experiences are a promising way to broaden participation in computer architecture research and have been shown to improve student learning, engagement, and retention. These outcomes can be more profound and lasting if students experience research early. However, there are many barriers to early research in computer architecture some of which include the gap between pedagogy and research, the lower emphasis on hardware design compared to software in first year courses, and the lack of online resources. We propose lowering these barriers through a methodical approach by involving undergraduates in early research and by creating freely available and innovative educational tools for designing hardware.We present the experience of a team of undergraduate students with research over one academic year using a Python hardware description language, PyRTL. PyRTL was developed to enable early entry into digital design. Its overarching goals are simplicity, usability, clarity, and extensibility, a stark contrast to traditional languages like Verilog and VHDL that have a steep learning curve. Instead of introducing traditional languages early in the undergraduate curriculum, PyRTL takes the opposite approach, which is to build on what students already know well: a popular programming language (Python), software design patterns, and software engineering principles. The students conducted their research in the context of the Early Research Scholars Program (ERSP), a program designed to expand access to research among women and underrepresented minority students in their second year through a well designed support structure.

gemOS: Bridging the Gap between Architecture and Operating System in Computer System Education

Abstract: Providing adequate exposure to architecture and OS interfaces can enable the students with better understanding of the concepts and increase their interest towards research problems crossing the hardware-software boundaries. Moreover, a framework to explore possible enhancements spanning across the architecture and operating system (OS) layers can be very useful for researchers. The existing tools and techniques used to teach system courses like OS and Computer Architecture serve the objective of respective courses to a large extent. However, exploration crossing the hardware and OS boundaries is particularly difficult due to lack of proper teaching infrastructure integrating the two layers. In this paper, we propose to use a specialized OS executing on the Gem5 full system simulator as an alternate approach to explore the architecture and OS boundaries. Open source OSes like Linux are not suitable for this purpose simply because they are not designed to be used as teaching infrastructure, especially on a system simulator like Gem5. We propose gemOS, a simple OS for 64-bit X86 simulation platform provided by the Gem5 architectural simulator. Further, we propose a simple framework using gemOS along with Gem5 and show its utility towards understanding the OS and architecture interactions, and, show the quick prototyping support of the framework to implement innovative ideas spanning across the two layers. We present use-cases and examples to demonstrate the utility of the proposed framework as a teaching and research infrastructure.

Exposing Abstraction-Level Interactions with a Parallel Ray Tracer

Abstract: For students of any Computer Engineering program, attaining an integrated vision of the different abstraction levels is paramount to fully understand and exploit a computer system, especially when tough topics such as parallelism, concurrency, consistency, or atomicity are involved at the hardware-software frontiers. However, the structure of typical engineering programs leads to the creation of self-contained courses, where a single level of abstraction is studied and the overall picture is lost.This paper provides a practical approach to show actual interactions between abstraction levels. This is achieved by implementing multiple components of a parallel ray tracer from the algorithmic level of the tracer to the atomic instructions required to guarantee atomicity. The students implement the full project throughout laboratories of different courses. Each lab focuses on a single abstraction level, but shows students the interactions with the rest of the levels. In addition, the hardware and software requirements of the approach are introduced, leading to the conclusion that Raspberry Pi is a suitable single-board computer for this project. Finally, this work also includes a preliminary assessment study of the proposed approach through the analysis of pre/post surveys filled out by the students.

Parallel Computing At The Undergraduate Level: Lessons Learned and Insights

Abstract: All computing devices we currently use are parallel machines. This includes the whole range from portable devices to supercomputers. Until recently, parallel computing at the undergraduate level was considered an advanced elective topic in most computer science and engineering departments. If this continues, undergraduate students will not be competitive in the market. If they decide to go to graduate studies, they will be late in acquiring parallel computing skills.In this paper we discuss the challenges and insights in designing an undergraduate parallel computing course in computer science department. These insights stem from our experience in offering this course for six years, once per year.

An Emphasis on Memory and Processor Interactions in Undergraduate Computer Architecture Education

Abstract: This paper discusses an innovative set of laboratories that are designed for the Oklahoma State University computer architecture class. The class is a required class for computer engineering majors within the School of Electrical and Computer Engineering at Oklahoma State University. Five (5) laboratories are designed and students work in teams of two with emphasis on learning interactions between memory in the ARMv4 microrarchitecture.