Showing papers by "Amkor Technology published in 2010"

Semiconductor package including top-surface terminals for mounting another semiconductor package

Abstract: A semiconductor package including top-surface terminals for mounting another semiconductor package provides a three-dimensional circuit configuration that can provide removable connection of existing grid-array packages having a standard design. A semiconductor die is mounted on an electrically connected to a circuit substrate having terminals disposed on a bottom side for connection to an external system. The die and substrate are encapsulated and vias are laser-ablated or otherwise formed through the encapsulation to terminals on the top surface of the substrate that provide a grid array mounting lands to which another grid array semiconductor package may be mounted. The bottom side of the vias may terminate and electrically connect to terminals on the substrate, terminals on the bottom of the semiconductor package (through terminals) or terminals on the top of the semiconductor die. The vias may be plated, paste-filled, filled with a low melting point alloy and may have a conical profile for improved plating performance.

Intermetallic Compound Growth and Reliability of Cu Pillar Bumps Under Current Stressing

Abstract: Fine-pitch Cu pillar bumps have been adopted for flip-chip bonding technology. Intermetallic compound (IMC) growth in Cu pillar bumps was investigated as a function of annealing or current stressing by in situ observation. The effect of IMC growth on the mechanical reliability of the Cu pillar bumps was also investigated. It is noteworthy that Sn exhaustion was observed after 240 h of annealing when current stressing was not applied, and IMC growth rates were changed remarkably. As the applied current densities increased, the time required for complete Sn consumption became shorter. In addition, Kirkendall voids, which would be detrimental to the mechanical reliability of Cu pillar bumps, were observed in both Cu3Sn/Cu pillars and Cu3Sn/Cu under-bump metallization interfaces. Die shear force was measured for Cu pillar samples prepared with various annealing times, and degradation of mechanical strength was observed.

Fingerprint sensor package and method

Abstract: A fingerprint sensor package includes a flat surface having a dielectric protective coating protecting a sensing element of a fingerprint sensor and an electrically conductive bezel that discharges electrostatic discharge (ESD). Both the protective coating and the bezel can be colored to have desired colors. Accordingly, the flat surface can be colored as desired enhancing the attractiveness for consumer applications. Further, light emitting diodes are integrated into the fingerprint sensor package providing a visual feedback to the user that the user's fingerprint has been successfully sensed. Further, the fingerprint sensor package is formed using a high volume low cost assembly technique.

Dual laminate package structure with embedded elements

Abstract: An interconnect structure (i.e., an interposer) which is mounted and electrically connected to a bottom semiconductor package substrate either prior or subsequent to such bottom substrate being populate with one or more electronic components. Subsequently, a top semiconductor package substrate which may also be populated with one or more electronic components is mounted to the interposer, such that all of the electronic components are disposed between the top and bottom interposers. Thereafter, a suitable mold compound is injected between the top and bottom substrates, the mold compound flowing about the electronic components, between the BGA joints, and at least partially about the interposer, thus helping to lock the interposer in place in the completed semiconductor package.

Improving electromagnetic compatibility performance of packages and SiP modules using a conformal shielding solution

Abstract: High-speed digital and wireless devices radiate unintentional electromagnetic noise, which can affect the normal operation of other devices within the same system, causing intra-system electromagnetic interference (EMI) problems, or contribute to the total radiated EMI from the system, resulting in potential system-level EMI issues. PCB and system level shielding may alleviate the system-level EMI between wireless PCB board and the outside environment, but seldom prevent the intra-system EMI within the shielding enclosure. Package and System in Package (SiP) level shielding is desirable to shield the unintended radiation and protect the other circuits on board. Traditionally an external metal lid is employed to isolate the radiation from an IC, but the package cost and the size penalty due to the solder pads for shield attachment make the solution unattractive. In this paper, a new shielding technology for IC packages based on metal spray coating (conformal shielding) is presented. By spraying a conductive material on the sides of the package, a very thin metal layer is constructed around the top and four sides of a package. This very thin sprayed metal layer adds zero penalty to the package size and works similar to a solid metal shielding with very good shielding effectiveness; hence, it is suitable for wireless infrastructure, tele-communications, and high-speed digital applications.

Top feature package and method

Abstract: An electronic component package includes a substrate and an electronic component mounted to the substrate, the electronic component including a bond pad. A first antenna terminal is electrically connected to the bond pad, the first antenna terminal being electrically connected to a second antenna terminal of the substrate. A package body encloses the electronic component, the package body having a principal surface. An antenna is formed on the principal surface by applying an electrically conductive coating. An embedded interconnect extends through the package body between the substrate and the principal surface and electrically connects the second antenna terminal to the antenna. Applying an electrically conductive coating to form the antenna is relatively simple thus minimizing the overall package manufacturing cost. Further, the antenna is relatively thin thus minimizing the overall package size.

Below 45nm low-k layer stress minimization guide for high-performance flip-chip packages with copper pillar bumping

Abstract: In this paper, the FEM based various parametric studies such as packaging material and structural effects, under bump metallization and passivation structures and material property effects on the low k layer are investigated for the flip-chip packaging with Cu pillar interconnection. The results showed that the stress of the low k layer is directly concerned wirh the CTE mismatch between low k die and substrate constrained by Cu pillar and maximized at the bump near the die corner after flip chip attach process before underfill. The stress contour shows that the low k area is affected by both tensile stress and compressive stress. The experimentally inspected low k damaged area showed half moon shape which reveals the failure mode is closely related with the tensile stress near the Al to Cu pillar interface. The comparison results show that the Cu pillar has 20% higher stress than lead free solder and 40% than eutectic solder case. The structural DOE shows that the reducing flip-chip die and substrate thickness and also reducing passivation opening cases showed effective for reducing low k stress after flip chip attach. After underfill and mold or MUF only process, stress change of low k layer showed good agreement to the CTE variation of underfill or MUF which means thermal expansion of underfill / MUF is governing factor for low k stress for the after assembly. Compared with CUF, MUF which has lower CTE than CUF showed relatively lower stress on the low k layer. By applying optimized structure and material properties of package, UBM and passivation layers, the stress of the low k layer can be reduced to the relatively safe level where the stress is lower than the eutectic solder applied case of the reference structure.

Stacked semiconductor package and method of making same

Abstract: In accordance with the present invention, there is provided multiple embodiments of a semiconductor package including two or more semiconductor dies which are electrically connected to an underlying substrate through the use of conductive wires, some of which may be fully or partially encapsulated by an adhesive or insulating layer of the package. In a basic embodiment of the present invention, the semiconductor package comprises a substrate having a conductive pattern disposed thereon. Electrically connected to the conductive pattern of the substrate are first and second semiconductor dies. The first semiconductor die and a portion of the substrate are covered by an adhesive layer. The second semiconductor die, the adhesive layer and a portion of the substrate are in turn covered by a package body of the semiconductor package.

Limitations of Norris-Landzberg equation and application of damage accumulation based methodology for estimating acceleration factors for Pb free solders

Abstract: With the increasing use of Pb free solder in Electronic assemblies the estimation of their reliability under field use conditions is becoming important. The acceleration factor for solder depends on delta T, dwell times, ramp rates, actual values of temperature extremes, and the type of package. During the last few years, a number of papers have been published to determine the acceleration factors using Norris-Landzberg equation by varying some of these parameters. However, no consistent Norris-Landzberg parameters have been found yet for SnAgCu solders. This paper seeks to relate the field life with accelerated life by using simulations and a damage accumulation methodology. It is shown that the damage accumulation process in solder joints is much more complex to be captured by a simplified equation, such as Norris-Landzberg equation. The data presented here also shows that the acceleration factors depend on the package type and basing reliability requirement on accelerated test conditions, e.g., 1000 cycles for −40 to 125°C, irrespective of package type might preclude a package for a certain application even though the package might pass field level reliability requirements.

Interfacial Reaction Effect on Electrical Reliability of Cu Pillar/Sn Bumps

Abstract: Thermal annealing and electromigration (EM) tests were performed with Cu pillar/Sn bumps to understand the growth mechanism of intermetallic compounds (IMCs). Annealing tests were carried out at both 100°C and 150°C. At 150°C, EM tests were performed using a current density of 3.5 × 104 A/cm2. The electrical failure mechanism of the Cu pillar/Sn bumps was also investigated. Cu3Sn formed and grew at the Cu pillar/Cu6Sn5 interface with increasing annealing and current-stressing times. The growth mechanism of the total (Cu6Sn5 + Cu3Sn) IMC changed when the Sn phase in the Cu pillar/Sn bump was exhausted. The time required for complete consumption of the Sn phase was shorter during the EM test than in the annealing test. Both IMC growth and phase transition from Cu6Sn5 to Cu3Sn had little impact on the electrical resistance of the whole interconnect system during current stressing. Electrical open failure in the Al interconnect near the chip-side Cu pillar edge implies that the Cu pillar/Sn bump has excellent electrical reliability compared with the conventional solder bump.

Stackable package and method

Abstract: A stackable package is placed within a mold during an encapsulation operation. A compliant surface, e.g., of a compliant film, of the mold is pressed down on upper interconnection balls of the stackable package to force upper portions of the upper interconnection balls into the mold. However, lower portions of the upper interconnection balls are exposed within a space between the compliant surface and a substrate of the stackable package. The space is filled with a dielectric material to form a package body. The package body is formed while at the same time exposing the upper portions of upper interconnection balls from the package body in a single encapsulation operation. By avoiding selective removal of the package body to expose the upper interconnection balls, the number of operations as well as cost to manufacture the stackable package is minimized.

Shielded electronic component package and method

Abstract: An electronic component package includes a substrate having a first surface, an electronic component mounted to the substrate, traces on the first surface, a terminal on the first surface, and a solder mask on the first surface. The solder mask includes a solder mask opening exposing the terminal. An electrically conductive coating and/or conductive coating feature is formed on the solder mask and extends into the solder mask opening to contact and be electrically connected to the terminal. The conductive coating may be grounded to shield the electronic component from electromagnetic interference (EMI). Further, the conductive coating provides a ground plane for the traces facilitating impedance matching of signals on the traces. In addition, the conductive coating has a high thermal conductivity thus enhancing heat dissipation from the electronic component. The conductive coating feature can be used as a conductive path to transmit electrical signals and/or to form circuit patterns that can be used as passive devices.

Flex circuit package and method

Abstract: A flex circuit package includes a package body enclosing an electronic component and a first surface of the substrate. Columns are physically and electrically connected to first traces of the substrate, the columns extending through the package body. A flexible circuit connector has first terminals connected to the columns. The flexible circuit connector further includes second terminals that provide an electrical interconnection structure for electrical connection to a second electronic component structure. By connecting the flexible circuit connector to the columns extending through the package body, special routing of traces of the substrate of the flex circuit package to provide an interface for the flexible circuit connector is avoided.

Semiconductor device having overlapped via apertures

Abstract: Disclosed is a semiconductor device having overlapped via apertures formed in an encapsulant to outwardly expose solder balls. When different types of semiconductor devices are electrically connected to the solder balls through the overlapped via apertures, flux or solder paste is unlikely to contact sidewall portions of the overlapped via apertures. Therefore, different types of semiconductor devices can be mounted with improved efficiency.

Light emitting diode (LED) package and method

Abstract: A method of forming a light emitting diode (LED) package includes mounting a LED structure to a carrier, overmolding the LED structure in a package body, backgrinding the package body to expose the LED structure, removing the carrier, and forming a redistribution layer (RDL) buildup structure comprising a RDL circuit pattern coupled to a LED of the LED structure. The LED package is formed without a substrate in one embodiment. By forming the LED package without a substrate, the thickness of the LED package is minimized. Further, by forming the LED package without a substrate, heat removal from the LED is maximized as is electrical performance. Further still, by forming the LED package without a substrate, the fabrication cost of the LED package is minimized.

Through via nub reveal method and structure

Abstract: A method includes applying a backside passivation layer to an inactive surface of an electronic component and to enclose a through via nub protruding from the inactive surface. The method further includes laser ablating the backside passivation layer to reveal a portion of the through via nub. The backside passivation layer is formed of a low cost organic material. Further, by using a laser ablation process, the backside passivation layer is removed in a controlled manner to reveal the portion of the through via nub. Further, by using a laser ablation process, the resulting thickness of the backside passivation layer is set to a desired value in a controlled manner. Further, by using a laser ablation process, the fabrication cost is reduced as compared to the use of chemical mechanical polish.

TIM selection methodology for high power flip chip packages

Abstract: Flip-chip packages are currently used for various applications such as desktop computers, servers, gaming, telecommunications, etc. Due to tremendous demand of die functionality, the power levels and more importantly the die heat-flux densities are drastically increasing, thus customers are constantly pushing packaging industries to lower thermal impedance of TIM for very high power flip chip packages. To achieve the target, TIM formulation focuses on filler type, size, loading, etc. Typically low modulus gel and grease type TIM are filled with Al 2 O 3 , Ag, Ga, Al, etc filler. Fillers are designed for high-performance, and high power application. The cross-linking properties of gel or grease type TIM should have enough strength so it can comfortably overcome squeeze or pump-out issue during highly accelerated package reliability tests. Package designers typically focus more on the thermal issues for TIM performance evaluation, characterization, and formulation, but there is not much study available [2–9] on TIM degradation in the packages and its actual thermal performance. Costly gel, grease, or solder polymer type materials have very good thermal properties, but during actual package reliability test sometimes they perform poorly due to excessive voids, pump-out, interface delamination, and other degradation issues [1]. This study started to meet more demanding thermal solutions by maintaining comprehensive TIM selection methodology with standard testing processes and materials to quantify future thermal load. While thermal performance is the primary target, mechanical vs thermal performance tradeoffs are investigated through extensive package reliability analysis for high power flip chip packages.

A novel method for strip level warpage simulation of PoP package during assembly

Abstract: Strip level warpage is important for improving package manufacturing processes yield. In addition, the process induced warpage in strip level can be one of the major contributors to package level warpage variation at end of line after singulation. However, not many studies have been conducted so far in the area of strip level warpage measurement and simulation due to some limitations. In this paper, shadow moire method was investigated to measure the warpage of the entire strip at elevated temperatures. Technical issues related to measuring samples with size as large as a strip in shadow moire, such as temperature uniformity, were fully evaluated. A super element sub-structuring simulation methodology was proposed and investigated to model strip level warpage in order to capture all the package details and substrate signal layer trace structures while keeping the whole strip model at a reasonable size for solution efficiency. Through this measurement and simulation study, it was found that (1) a strip could show warpage dominated in strip length direction or in width direction. More importantly, this dominant direction could switch when temperature ramped up from room temperature to reflow temperature. (2) Different window blocks in the same strip could have different warpage characteristics. The inner window blocks had warpage dominated in width direction at all temperatures, but the outer window blocks changed the dominant warpage direction from length to width direction as temperature increased. As a result, it was concluded that a whole strip must be measured or simulated rather than just one window block for strip level warpage characterization. (3) Unlike package level warpage model, nonlinear geometry effect was very significant for strip level model. This effect must be taken into account in the model in order to obtain accurate simulation results. (4) For the strip studied here, simulation results showed lower copper density in the substrate helped reduce strip warpage. In addition, the effect of copper balance among 4 signal layers was also evaluated.

Stackable treated via package and method

Abstract: A method of forming a stackable treated via package includes coupling interconnection balls to terminals. The interconnection balls are encapsulated in a package body. Via apertures are formed in the package body to expose the interconnection balls. The interconnection balls are treated to form treated interconnection balls comprising treated surfaces. The treated interconnection balls of the stackable treated via package enhance bonding with interconnection balls of a stacked electronic component package thus maximizing yield.

System and method for lowering contact resistance of the radio frequency (RF) shield to ground

Abstract: A semiconductor device has a substrate having a plurality of metal traces. A die is electrically attached to a first surface of the substrate. A first plurality of segmented metal traces is formed around a perimeter of the first surface of the substrate, wherein an end section of the first plurality of segmented metal traces is exposed. A mold compound is used for encapsulating the semiconductor device. A first metal plating is formed on a top terminal end section of the first plurality of segmented metal traces. The first metal plating is spread to at least one of the mold compound or the exposed end sections of the first plurality of segmented metal traces. A conductive coating is applied to the mold compound, the exposed end sections of the first plurality of segmented metal traces and to the first metal plating.

Semiconductor package thermal tape window frame for heat sink attachment

Abstract: The present invention is directed to a semiconductor packaging solution wherein a high K thermal material such as a grease or gel is placed in a controlled thin bond line between the semiconductor die of the package and a heat sink in a direct manner using a thermal tape window frame as a low cost mechanical attachment mechanism. As the main thermal dissipation path is between the backside of the semiconductor die and the heat sink, a high K TIM material can be used to maximize thermal dissipation in a manner that does not require expensive mechanical attachment methods.

Factors affecting electromigration and current carrying capacity of FC and 3D IC interconnects

Abstract: Electromigration (EM) failure in flip-chip bumps has emerged as a major reliability concern due to potential elimination of Pb from flip-chip bumps and a continuous drive to increased IO density resulting in a reduction of bump pitch and size. Additionally, the rapid development and implementation of 3D IC structures is introducing new interconnects (u-bumps, RDL, microvias, and TSVs) at a much finer geometries, raising concerns about electromigration and current carrying capacity of these interconnects.

Semiconductor device having through electrodes protruding from dielectric layer

Abstract: A semiconductor device and a manufacturing method thereof are provided. In one embodiment of the manufacturing method of the semiconductor device, a through electrode is formed on a semiconductor die, and a dielectric layer such as a photopolymer is coated on the through electrode to cover the through electrode. Under exposure is performed on the dielectric layer, thereby partially removing the dielectric layer by development. As a result, a top end of the through electrode is exposed to the outside or protrudes through the dielectric layer. The dielectric layer remaining on the top end of the through electrode may be removed by performing a plasma descum process, if needed.

Interface fracture toughness assessment of solder joints using double cantilever beam test

Abstract: In the current work, a test scheme to evaluate solder joint interface fracture toughness using double cantilever beam (DCB) test has been successfully demonstrated. The obtained results, in terms of critical energy release rate, predict the joint failure based on the principle of fracture mechanics. The results can be used as a materials property in the reliability design of various types of solder-ball joined packages. DCB specimens made of 99.9 wt% copper were selected in the current work. Eutectic Sn-37Pb and lead-free Sn-3.5Ag-0.5Cu solders were used to join two pieces of the copper beams with controlled solder thickness. The test record showed steady propagation of the crack along the solder / copper interface, which verifies the viability of such a testing scheme. Interface fracture toughness for as-joined, extensively-reflowed and thermally aged samples has been measured. Both the reflow treatment and the thermal aging lead to degradation of the solder joint fracture resistance. Reflow treatment was more damaging as it induces much faster interface reaction. Fractographic analysis established that the fracture has a mixed micromechanism of dimple and cleavage. The dimples are formed as a result of the separation between the hard intermetallic compound (IMC) particles and the soft solder material, while the cleavage is formed by the brittle split of the IMCs. When the IMC thickness is increased due to extended interface reaction, the proportion of IMC cleavage failure increases, and this was reflected in the decrease of the critical energy release rate.

Conductive polymer lid for a sensor package and method therefor

Abstract: A semiconductor device has a base substrate having a plurality of metal traces. A conductive polymer cover is provided having an opening. The conductive polymer cover forms a cavity when attached to the base substrate. At least one die is attached to an interior surface of the conductive polymer cover and positioned over the opening. The conductive polymer cover and the at least one die are electrically coupled to metal traces on the first surface of the base substrate.

Integrated passive device structure and method

Abstract: An integrated passive device (IPD) structure includes an electronic component having an active surface and an opposite inactive surface. The IPD structure further includes a passive device structure extending through the electronic component between the active surface and the inactive surface and having a portion(s) formed on the active surface, the inactive surface, or both the active and inactive surfaces. Accordingly, the IPD structure includes the functionality of the electronic component, e.g., an integrated circuit chip, and of the passive device structure, e.g., one or more capacitors, resistors, inductors, or surface mounted components. By integrating the passive device structure with the electronic component to form the IPD structure, separate mounting of passive component(s) to the substrate is avoided this minimizing the substrate size.

Top port MEMS microphone package and method

Abstract: A top port MEMS microphone package includes a substrate having a back volume expanding aperture therein. A MEMS microphone electronic component is mounted to the substrate directly above the back volume expanding aperture such that an aperture of the MEMS microphone electronic component is in fluid communication with the back volume expanding aperture. A lid having a lid cavity is mounted to the substrate. The back volume expanding aperture couples the aperture of the MEMS microphone electronic component to the lid cavity. By coupling the lid cavity to the aperture with the back volume expanding aperture, the resulting back volume is essentially the size of the entire top port MEMS microphone package. In this manner, the noise to signal ratio is minimized thus maximizing the sensitivity of the top port MEMS microphone package as well as the range of applications.

Heat spreader package and method

Abstract: A heat spreader package includes a substrate having a first surface, first traces on the first surface of the substrate, and an electronic component having an inactive surface mounted to the first surface of the substrate. The electronic component further includes an active surface having bond pads. Bond wires electrically connect the bond pads to the first traces. An inverted pyramid heat spreader includes a first heatsink, a first heatsink adhesive directly connecting the first heatsink to the active surface of the electronic component inward of the bond pads, a second heatsink having an absence of active circuitry, and a second heatsink adhesive directly connecting a first surface of the second heatsink to the first heatsink. The second heatsink adhesive is a dielectric directly between the bond wires and the second heatsink that prevents inadvertent shorting between the bond wires and the second heatsink.