Showing papers by "Cadence Design Systems published in 2002"

Characterization and verification for integrated circuit designs

Abstract: Variations are characterized in feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that produces topographical variation in the integrated circuit, the variations in feature dimension being caused by the topographical variations. The process includes lithography or etch. Predicted characteristics are verified to conform to the design, the characteristics including feature dimensions or electrical characteristics. A process is selected for use in fabricating the integrated circuit based on the relative predicted variations. Chip-level features of a design of an integrated circuit are verified for manufacture within focus limitations of a lithographic tool. Whether a design of a level of an integrated circuit can be lithographically imaged in accordance with the design is predicted, and if it cannot be, the design or processing parameters are adjusted so that it can be.

Dummy fill for integrated circuits

Abstract: A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.

Adjustment of masks for integrated circuit fabrication

Abstract: A pattern-dependent model is used to predict characteristics of an integrated circuit that is to be fabricated in accordance with a design by a process. The process includes (a) a fabrication process that will impart topographical variation to the integrated circuit and (b) a lithography or etch process, the lithography or etch process using a mask produced from the design. The lithography or etch process and the fabrication process interact to cause the predicted characteristics to differ from the design. The mask is adjusted in response to characteristics predicted by the model, to reduce the effect of the interacting of the lithography or etch process and the fabrication process. A location on an integrated circuit is predicted for which a lithography tool would not produce a satisfactory feature dimension without a degree of adjustment of the tool during fabrication to accommodate a focus limitation of the tool, and the design of at least one mask derived from the design is adjusted to enable the lithography tool to produce a satisfactory feature dimension at the locations. A virtual adjustment is effected of a distance of a lithographic tool from a location in a region of a wafer, the virtual adjustment being effected by using a mask having a mask layout that has been generated based on a pattern-dependent model prediction that the location in the region of the wafer would not otherwise have a satisfactory feature dimension due to a focus limitation of the lithographic tool. A pattern-dependent model is used to predict topography variations that will occur in an integrated circuit as a result of processing up to a predetermined lithographic process step, and designs of masks used in the lithographic process step are adjusted to accommodate the topography variations.

Guaranteed passive balancing transformations for model order reduction

Abstract: The major concerns in state-of-the-art model reduction algorithms are: achieving accurate models of sufficiently small size, numerically stable and efficient generation of the models, and preservation of system properties such as passivity. Algorithms such as PRIMA generate guaranteed-passive models, for systems with special internal structure, using numerically stable and efficient Krylov-subspace iterations. Truncated balanced realization (TBR) algorithms, as used to date in the design automation community, can achieve smaller models with better error control, but do not necessarily preserve passivity. In this paper we show how to construct TBR-like methods that guarantee passive reduced models and in addition are applicable to state-space systems with arbitrary internal structure.

Method and system for chip design using remotely located resources

Abstract: A multi-faceted design platform (104) acts as a tool for front-end hardware IC designers who design complex core base System on Chip. The design platform (104) uses a network such as the Internet (230) to search and gain access to previously designed virtual core blocks. The design platform (104) provides a means to select (306) and transfer (308) all relevant information regarding the selected virtual core blocks and allows the designer to immediately incorporate the virtual core block into the new SoC design. The design platform (104) further generates the appropriate source code files (320) for immediate use with a plurality of known verification tools to verify both the integration and connectivity of the virtual core blocks as well as the basic functionalities of the SoC design.

Block based design methodology with programmable components

Abstract: A method for designing a circuit block includes the steps of selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, at least one of said circuit blocks being programmable; collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method; accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk; upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks (FEA); and, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, in compliance with the criteria and modified constraints without changing the selected circuit block and the processing method.

Molecular electronics: devices, systems and tools for gigagate, gigabit chips

Abstract: New electronics technologies are emerging which may carry us beyond the limits of lithographic processing down to molecular-scale feature sizes. Devices and interconnects can be made from a variety of molecules and materials including bistable and switchable organic molecules, carbon nanotubes, and, single-crystal semiconductor nanowires. They can be self-assembled into organized structures and attached onto lithographic substrates. This tutorial reviews emerging molecular-scale electronics technology for CAD and system designers and highlights where ICCAD research can help support this technology.

Electronic design for integrated circuits based on process related variations

Abstract: An electronic design is generated for an integrated circuit that is to be fabricated in accordance with the electronic design by a process that will impart topographically induced feature dimension variations to the integrated circuit. The generating includes adjusting the electronic design based on predictions of topographical and topographical-related feature dimension variations by a pattern-dependent model. An RC extraction tool is used in conjunction with the generating and adjusting of the electronic design. The process includes a fabrication process that will impart topographical variation to the integrated circuit and a lithography or etch process. Placement attributes for elements of the integrated circuit are determined.

On-chip RF isolation techniques

Abstract: On-chip isolation is a function of many interdependent variables. This paper uses industry examples to highlight the isolation impacts of technology - substrate doping levels and triple wells, grounding/guard rings, shielding, capacitive decoupling, and package inductance.

Hierarchically structured logging for computer work processing

Abstract: A work request is processed and interpreted to automatically establish job data structures associated with jobs constituent to the work and data storage structures associated with tasks constituent to the work. Further, parent-child relationships between jobs, sub-jobs and tasks are automatically established based on interpreting the work request. Once tasks are executed, log information related thereto is stored in respective data storage structures, for access and rendering upon request. Each data storage structure stores log information pertaining only to a respective task. In an embodiment, in response to receiving a request to delete a particular job, the particular job and all of its progeny sub-jobs and tasks are deleted. The work request does not include explicit commands to establish the job data and data storage structures, nor to store the log information in the data storage structures. Generally, structured work requests based on a job request language and interpreted by work management application layer provide the foregoing functionality. In embodiments, a representation of a job data structure and its constituent sub-job and/or data storage structures are rendered, along with linking mechanisms between various levels of the overall work aggregation hierarchy that is implied in an associated work request. The links can be used to traverse the hierarchy to easily access and view log information stored in data storage structures.

An 852/spl times/600 pixel OLED-on-silicon color microdisplay chip using CMOS sub-threshold-voltage-scaling current driver

Abstract: An 852/spl times/600/spl times/3-pixel, organic light-emitting diode (OLED)-on-silicon, color microdisplay utilizing a subthreshold-voltage-scaling method is presented. The pixel current is modulated between 250 pA and 25 nA. With a pixel pitch of 5/spl times/15 /spl mu/m/sup 2/, the display contains 1.5 million individually addressable pixels sampling video signals at a maximum rate of 56.25 MHz, supports 15 video modes, and displays as many as 16 million colors. The 16.28/spl times/14.2 mm/sup 2/ monolithic display is implemented in a commercially available, 0.35-/spl mu/m, single-poly four-metal 3.3 V/4.0 V CMOS process with the 10 million transistor system consuming 300 mW for PC applications. The SVGA+ active matrix OLED system provides a complete, integrated, analog interface microdisplay solution with minimal external components. DC-coupled RGB inputs with separate external vertical and horizontal synchronization inputs are accepted in accordance with the VESA VSIS standard. A fourth analog input is provided for composite monochrome, compatible with the SMPTE-170 standard.

Mechanism for managing parallel execution of processes in a distributed computing environment

Abstract: According to one aspect, a work request that specifies first and second jobs is received. The first job comprises a first task and the second job comprises a second task. The work request is processed to automatically determine whether the jobs have any dependencies that have not been satisfied. In response to a determination that the jobs have no dependencies that have not been satisfied, the jobs are caused to be executed in parallel. As a default manner of operation, the tasks included in each respective job are collectively executed in parallel, whereas tasks within a given job are not executed in parallel. In an embodiment, the tasks are executed on one or more servers of a group of networked servers.

Algorithms for minimizing standby power in deep submicrometer, dual-V/sub t/ CMOS circuits

Abstract: Addresses the problem of delay constrained minimization of standby power of CMOS digital circuits that are implemented with dual-V/sub t/ technology. The availability of two or more threshold voltages on the same chip provides a new opportunity for circuit designers to make tradeoffs between power and delay. Three efficient algorithms that operate on a gate level netlist are described. Each algorithm assigns one of two threshold voltages (high and low V/sub t/) to each transistor so that the standby power dissipation is minimized without violating a user specified delay constraint. Experimental results on the MCNC91 benchmark circuits show that up to one order of magnitude power reduction can be achieved without any increase in delay when compared to the configuration in which all devices are at the low V/sub t/.

Secure inter-company collaboration environment

Abstract: An environment is described in which multiple companies can securely collaborate on a design or other project. The environment includes a set of resources residing on a set of one or more utility servers maintained by a first company, an access control mechanism for controlling access to the set of resources, a secure network connection between the set of utility servers and a second company, and a remote controller for remotely viewing, by an authorized individual from the second company, a user interface of an application while an authorized individual from the first company is executing the application on the set of utility servers. The secure network connection includes a secure association mechanism for establishing a secure association between participating parties, a virtual point-to-point network connection for transmitting data between associated parties, and an encryption/decryption mechanism.

Mechanism for managing execution of interdependent aggregated processes

Abstract: Dependencies can be specified between jobs that are constituent to a unit of work, which are automatically determined or identified by processing a work request that defines the work. For example, a second job can be specified as depending on a first job meeting a particular condition. Furthermore, sub-works of the second job are not scheduled for execution until the first job has met the condition, thus allowing the second job to be placed into an active state. First, a work request is received, which specifies a first job that includes a first set of sub-works and a second job that includes a second set of sub-works. The work request is interpreted and processed to determine that the second job has the dependency on the first job. The first job is placed into an active state to enable the first sub-works to be scheduled for execution. The second job is placed in a pending state and it is determined whether the first job has met the condition. If it has, the second job is placed into an active state and the second sub-works are scheduled for execution. In an embodiment, the first job is caused to be executed without initiation by the second job, that is, its dependent job.

Method and apparatus for concurrent engineering and design synchronization of multiple tools

Abstract: Concurrent engineering among multiple design groups is facilitated by maintaining design changes in a data model of a design being developed. Design changes for each group are made from a baseline design. Changes are tracked by maintaining change information from all but an owner of the original baseline design. Changes are synchronized by identifying owner and non-owner changes and merging the changes to produce a final design. Since non-owner changes are tracked, the baseline design is not needed in synchronization. Preferably the invention is applied to electronic designs made by multiple design groups at geographically diverse locations. The invention may also be applied to any system where configuration management of developed software, parts, or any design is needed.

Integrated circuit metrology

Abstract: Sites to be measured on a device that is to be fabricated using at least one fabrication process, are selected based on a pattern-dependent model of the process. A metrology tool to measure a parameter of a semiconductor device includes a control element to select sites for measurement based on a pattern dependent model of a process with respect to the device. Problematic areas, within a chip or die and within a wafer, are identified that result from process variation. The variation is identified and characterized, and the location of each site is stored. The sites may be manually entered into a metrology tool or the method will automatically generate a measurement plan. Process variation and electrical impact are used to direct the measurement of within-die and wafer-level integrated circuit locations.

UML for Embedded Systems Specification and Design: Motivation and Overview

Abstract: The specification, design and implementation of embedded systems demands new approaches which go beyond traditional hardware-based notations such as HDLs. The growing dominance of software in embedded systems design requires a careful look at the latest methods for software specification and analysis. The development of the Unified Modeling Language (UML), and a number of extension proposals in the realtime domain holds promise for the development of new design flows which move beyond static and traditional partitions of hardware and software. However, UML as currently defined lacks several key capabilities. In this paper, we will survey the requirements for system-level design of embedded systems, and give an overview of the extensions required to UML that will be dealt with in more detail in the related papers. In particular, we will discuss how the notions of platform-based design intersect with a UML based development approach.

Mechanism for managing execution environments for aggregated processes

Abstract: Workspace definitions, which define an execution environment, can be associated with jobs. A work request is processed to automatically determine that tasks that are progeny of a given job inherit the association with the workspace definition, and therefore, that the tasks should be executed using the execution environment defined in the workspace definition. However, different execution environments can be defined for progeny of a given parent job, essentially overriding the inheritance from the parent job. According to an embodiment, a set of resources associated with an execution environment is configured such that the resources are accessible by two or more computers of a group of networked computers, such as a server farm, without requiring configuring duplicate sets of the resources. Furthermore, in a server farm computing environment, an execution environment associated with one or more jobs is not reliant on being created on any given computer of the server farm.

Layouts with routes with different spacings in different directions on the same layer, and method and apparatus for generating such layouts

Abstract: Some embodiments of the invention provide a method of routing nets in a multi-layer integrated-circuit (“IC”) layout. For each particular net in a set of nets, the method specifies different spacing constraints for routing the particular net in different directions on the same layer. It then defines a particular route for each particular net in the set of nets, where the spacing between at least one particular route and an item adjacent to the route in the layout is different in the different directions on the same layer.

Passive Constrained Rational Approximation Algorithm Using Nevanlinna-Pick Interpolation

Abstract: As system integration evolves and tighter design constraints must be met, it becomes necessary to account for the non-ideal behavior of all the elements in a system. For high-speed digital, and microwave systems, it is increasingly important to model previously neglected frequency domain effects. In this paper, results from Nevanlinna-Pick interpolation theory are used to develop a bounded real matrix rational approximation algorithm. A method is presented that allows for the generation of guaranteed passive rational function models of passive systems by approximating their scattering parameter matrices. Since the order of the models may in some cases be high, an incremental fitting strategy is also proposed that allows for the generation of smaller models while still meeting the required passivity and accuracy requirements. Results of the application of the proposed method to several real-world examples are also shown.

Method and apparatus for placing circuit modules

Abstract: Some embodiments of the invention are placers that use diagonal lines in calculating the costs of potential placement configurations. For instance, some embodiments estimate the delay cost of a placement configuration by accounting for the potential use of diagonal wiring in the layout. Some of these embodiments derive the delay cost from an estimate of the wirelength needed to route the nets in the region.

Method and apparatus for routing with independent goals on different layers

Abstract: Some embodiments of the invention provide a method of routing. The method selects a net with a set of routable elements in a multi-layer layout region. In some embodiments, the method identifies a route for the net based on different congestion goals on different layers. In other embodiments, the method identifies a route for the net based on different congestion goals between different layer pairs. In some embodiments, the method identifies a route for the net based on both the different congestion goals on different layers and between different layer pairs.

Method and apparatus for pre-computing routes for multiple wiring models

Abstract: Some embodiments provide a method of pre-computing routes for nets in a region of an integrated circuit (“IC”) layout. The method initially defines a set of partitioning lines for partitioning the region into a plurality of sub-regions during a routing operation. For a particular set of potential sub-regions, the method then identifies a first set of routes based on a first wiring model and a second set of routes based on a second wiring model. Each identified set of routes traverses the particular set of potential sub-regions. The method then stores the identified routes.

Quadratic programming method for eliminating cell overlap and routing congestion in an ic layout

Abstract: To help eliminate overlapping cell placements or to reduce routing congestion in an IC layout wherein cells are integer multiples of a standard size cell unit, the layout is organized into an array of rectangular blocks, each having capacity to accommodate several cell units. A separate equation is established for each block relating a sum of a set of flow variables to an “overflow factor”. Each flow variable of the equation for each block corresponds to a separate one of that block's neighboring blocks and represents an estimated number of cell units that must be moved to or received from the corresponding neighboring block to eliminate overlapping cell placements or routing congestion within the block. The overflow factor for each block represents an estimated total number of cell units the block must pass into its neighboring blocks or an estimated maximum number of cell units it may receive from its neighboring blocks in order to eliminate cell overlap or routing congestion in all blocks. A solution to the set of equations is then selected to obtain values of flow variables which, when subsequently used to guide cell relocation, substantially reduces likelihood of cell overlap or routing congestion while substantially minimizing disturbance to the layout.

Method and apparatus for storing routes for groups of related net configurations

Abstract: Some embodiments of the invention provide a method that pre-computes routes for groups of related net configurations. These routes are used by a router that uses a set of partitioning lines to partition a region of a design layout into a plurality of sub-regions. The method identifies groups of related sub-region configurations. For each group, the method stores a base set of routes. For each configuration in each group, the method also stores an indicia that specifies how to obtain a related set of routes for the particular configuration from the base set of routes stored for the configuration's group.

Methodologies and tools for pipelined on-chip interconnect

Abstract: As processes shrink, gate delay improves much faster than the delay in long wires. Therefore, the long wires increasingly determine the maximum clock rate, and hence performance, of more and more chips. One solution to this problem is to pipeline the global interconnect, enabling the whole chip to run at the speed of local operations. While known to work well, this optimization is seldom used because of practical difficulties - it is hard to change the RTL, test vectors become invalid, and it's hard to prove correctness of any changes. Here we look at some ways these difficulties could be overcome.

Method and apparatus for pre-computing routes

Abstract: Some embodiments provide a method of pre-computing routes for nets in a region of a circuit layout. The method initially defines a set of partitioning lines for partitioning the region into a plurality of sub-regions during a routing operation. The method then identifies a primary set of sub-regions that has more than one sub-region. It then determines whether the primary set of sub-regions is an open set that has a sub-region that is not adjacent to any other sub-region in the set. If the primary set of sub-regions is not an open set, the method identifies a route that connects the sub-regions in the primary set, and stores the identified route for the primary set of sub-regions. On the other hand, if the primary set of sub-regions is an open set, the method identifies a connection set of sub-regions that when combined with the primary set forms a closed set of sub-regions that (i) does not have any sub-region that is not adjacent to another sub-region in the closed set, and (ii) can be traversed by a minimum tree route that connects each sub-region in the connection set to at least two other sub-regions in the primary and connection sets of sub-regions. For the primary set of sub-regions, the method then stores at least either the connection set of sub-regions or the closed set of sub-regions.

Method for estimating peak crosstalk noise based on separate crosstalk model

Abstract: Crosstalk noise peaks in output signals of nets of an integrated circuit layout design are estimated by first processing the design to estimate resistances and capacitances of the nets. The design is then processed to identify each aggressor net having at least one section that is proximate to a section of a victim net. A separate aggressor model is then generated for each proximate aggressor net section, the aggressor model including a current source and a capacitor. The design is then processed to identify each victim net that is proximate any aggressor net and a separate crosstalk model is generated for each identified victim net. The crosstalk model for each victim net includes the victim net's estimated resistances and capacitances and incorporates the aggressor model of each aggressor net section that is proximate to a section of the identified victim net. The crosstalk model for each identified victim net is then evaluated to determine a response to a signal applied as input to the victim net of a victim net output signal. The peak crosstalk noise in each identified victim net is estimated based on the response of the net's output signal.

Method and apparatus for table and HDL based design entry

Abstract: Views for signals and instances are provided in a table based design entry system. The signal view allows a designer to enter signals to be used in a design. The signals may be individually entered or imported from pre-defined or external packages of signals. The instance view allows the designer to enter components and to define connectivity of pins of the components to signals. The components may be entered individually or imported from predefined or external packages. An naming routines provides signal name generation and copying names of other components (e.g., pin names) to name the signals. Data entered into the table based entry system is checked for errors (duplicate names, syntax, etc.), and exported to other design tools for processes such as simulation, layout, etc.