Showing papers in "Microelectronics International in 2009"

Wire bonding using copper wire

Abstract: Purpose – This paper attempts to review recent advances in wire bonding using copper wire.Design/methodology/approach – Dozens of journal and conference articles published recently are reviewed.Findings – The problems/challenges such as wire open and short tail defects, poor bondability for stitch/wedge bonds, oxidation of Cu wire, strain‐hardening effects, and stiff wire on weak support structures are briefly analysed. The solutions to the problems and recent findings/developments in wire bonding using copper wire are discussed.Research limitations/implications – Because of page limitation of the paper, only a brief review is conducted. Further reading is needed for more details.Originality/value – This paper attempts to provide introduction to recent developments and the trends in wire bonding using copper wire. With the references provided, readers may explore more deeply by reading the original articles.

Polymer‐metal nano‐composite films for thermal management

Abstract: Purpose – The purpose of this paper is to present a novel nanostructured polymer‐metal composite film providing continuous all‐metal thermally conductive pathways, intended to meet future performance requirements on thermal interface materials (TIMs) in microelectronics packaging applications.Design/methodology/approach – Porous polymer structures with a thickness of approximately 100 μm were manufactured using electrospinning technology. Pressure‐assisted infiltration of low‐melting temperature alloy into the porous polymeric carrier resulted in the final composite film. Thermal performance was evaluated using an accurate and improved implementation of the ASTM D5470 standard in combination with an Instron 5548 MicroTester. Finally, a brief comparative study using three current state‐of‐the‐art commercial TIMs were carried out for reference purposes.Findings – Composite films with continuous all‐metal thermally conductive pathways from surface to surface were successfully fabricated. Thermal resistances ...

Effects of process variation in VLSI interconnects – a technical review

Abstract: Purpose – Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. The purpose of this paper is to provide a comprehensive overview of types and sources of all aspects of interconnect process variations.Design/methodology/approach – The impacts of these interconnect process variations on circuit delay and cross‐talk noises along with the two major sources of delays – parametric delay variations and global interconnect delays – have been discussed.Findings – Parametric delay evaluation under process variation method avoids multiple parasitic extractions and multiple delay evaluations as is done in the traditional response surface method. This results in significant speedup. Furthermore, both systematic and random process variations have been contemplated. The systematic variations need to be experimentally modeled and calibrated while the random variations are inherent fluctuations in process parameters due to any reason in manufacturing and h...

Chemical characterization of failures and process materials for microelectronics assembly

Abstract: Purpose – The purpose of this paper is to discuss the chemical characterization of failures and process materials for microelectronics assembly.Design/methodology/approach – The analytical techniques used for chemical structures and compositions including Fourier transform infrared spectrometer (FTIR), scanning electron microscopy, and energy‐dispersive X‐ray spectroscopy are conducted.Findings – The residues on the golden finger are identified to be the flux used in the assembly processes. Besides, the contaminants on the processed and incoming connector pins are verified to be polyamides (–CONH functional groups) from housing material's residue. Three liquid fluxes used in wave soldering are analyzed by their chemical structure. One flux showing the OH groups at 3430 cm−1 indicates higher acid contents. This consists with the acidic values specified by the supplier. Also, the solder mask under study has ever appeared peeled‐off issue. The FTIR spectra results indicated 62.2 percent degree of curing whil...

Fine and ultra‐fine pitch wire bonding: challenges and solutions

Abstract: Purpose – The purpose of this paper is to review recent advances in fine and ultra‐fine pitch wire bonding.Design/methodology/approach – Dozens of journal and conference articles published recently are reviewed.Findings – The problems/challenges such as possible wire sweep and decreased bonding strength due to small wire sizes, non‐sticking, metal pad peeling, narrow process windows, wire open and short tail defects are analysed. The solutions to the problems and recent findings/developments in fine and ultra‐fine pitch wire bonding are discussed.Research limitations/implications – Because of the page limitation, only brief discussions are given in this paper. Further reading is needed for more details.Originality/value – This paper attempts to provide an introduction to recent developments and the trends in fine and ultra‐fine pitch wire bonding. With the references provided, readers may explore more deeply by reading the original articles.

Analytical modeling for the estimation of leakage current and subthreshold swing factor of nanoscale double gate FinFET device

Abstract: Purpose – The aim of this paper is to formulate the effect of the process variation on various leakage currents and subthreshold swing factor in FinFET devices. These variations cause a large spread in leakage power, since it is extremely sensitive to process variations, which in turn results in larger temperature variations across different dies.Design/methodology/approach – Owing to large temperature variation within the die, the authors investigate the variation of various leakage currents with absolute die temperature.Findings – The results obtained on the basis of the model are compared and contrasted with reported numerical and experimental results. A close match was found which validates the analytical approach.Originality/value – The analytical modeling of subthreshold leakage current, subthreshold swing, gate leakage current and its variation with process parameters are carried out in this paper.

A proposed SRAM cell for low power consumption during write operation

Abstract: Purpose – Low power static‐random access memories (SRAM) has become a critical component in modern VLSI systems. In cells, the bit‐lines are the most power consuming components because of larger power dissipation in driving long bit‐line with large capacitance. The cache write consumes considerable large power due to full voltage swing on the bit‐line. The aim of the paper is to propose a new SRAM cell architecture to reduce the power consumption during write 0 and write 1 operation.Design/methodology/approach – The proposed circuit includes two tail transistors in the pull‐down path of inv‐A and inv‐B. The simulated results of the proposed cell is compared with Conventional 6T SRAM cell and zero‐asymmetric SRAM cell.Findings – The proposed SRAM cell consumes less power than the conventional SRAM cell during write operation. The write access delay is reported to be lower than conventional and ZA SRAMs in the proposed circuit. The read operation is similar to Conventional SRAM cell but due to tail transist...

Micro‐flow sensor for water using NTC thick film segmented thermistors

Abstract: Purpose – The purpose of this paper is to apply negative thermal coefficient (NTC) thick film segmented thermistors (TFSTs) in a micro‐flow sensor for water.Design/methodology/approach – A TFST is printed using NTC paste based on nickel manganite. The resistance of this thermistor is measured in a climatic chamber and the resulting curves are calibrated. A micro‐flow sensor is designed using a self‐heated segmented thermistor. The sensing principle is based on heat loss depending on the water flow intensity through the capillary. Water flow calibration is performed. The sensor sensitivity, inertia, and stability are analyzed.Findings – The micro‐flow sensor exhibits good stability, suitable sensitivity, and inertia for integral measurements of water flow.Practical implications – Advantages of a micro‐flow sensor using a TFST include low energy consumption, simple measuring procedure, and passive electronics.Originality/value – This paper describes initial work on a micro‐flow sensor for water using TFSTs.

Influence of solution acidity on composition, structure and electrical parameters of Ni‐P alloys

Abstract: Purpose – The purpose of this paper is to characterize electrical parameters of amorphous Ni‐P resistive layers used for fabrication of precise resistors.Design/methodology/approach – Ni‐P resistive layers were produced by the chemical process in water solution using Ni2 + and H2PO2− ions. The paper presents the results of the studies concerning the influence of bath acidity and conditions of thermal stabilization on the structure and temperature coefficient of resistance of Ni‐P alloy.Findings – The temperature coefficient of resistance of amorphous Ni‐P layers was found to depend significantly on the parameters of chemical metallisation process. It was stated that the changes of through‐casing resistivity versus the acidity of technological solution have roughly parabolic characteristics.Originality/value – In this paper, it was at first explained how the changes of the structure of Ni‐P resistive layers depend on their temperature coefficient of capacitance.

Microwave dielectric and attenuation properties of Ni0.7‐xCoxZn0.3Fe2O4 thick films

Abstract: Purpose – The aim of this paper is to investigate permittivity of nano structured Ni0.7‐xCoxZn0.3Fe2O4 thick films at microwave frequencies.Design/methodology/approach – Nanosized Ni0.7‐xCoxZn0.3Fe2O4 ferrites with x=0, 0.04, 0.08 and 0.12 were prepared by sucrose precursor technique using the constituent metal nitrates. Thick films of the ferrites were fabricated on alumina substrates by screen‐printing technique. Microwave dielectric constant (e′) and the loss factor (e″) for the thick films were measured by VSWR slotted section method in the 8‐18 GHz range of frequencies. Microwave attenuation properties were studied using a waveguide reflectometer set up.Findings – Both the e′ and e″ were found to vary with frequency and composition x. It is observed that, value of e′ increases with increase in x, due to the increase in bulk density and reduction in porosity of the material, that resulted due to the substitution of cobalt in Ni‐Zn ferrite. The microwave transmission loss offered by the thick films was...

A highly miniaturized wireless inertial sensor using a novel 3D flexible circuit

Abstract: Purpose – The purpose of this paper is to develop a highly miniaturized wireless inertial sensor system based on a novel 3D packaging technique using a flexible printed circuit (FPC). The device is very suitable for wearable applications in which small size and lightweight are required such as body area network, medical, sports and entertainment applications.Design/methodology/approach – Modern wireless inertial measurement units are typically implemented on a rigid 2D printed circuit board (PCB). The design concept presented here is based around the use of a novel planar, six‐faceted, crucifix or cross‐shaped FPC instead of a rigid PCB. A number of specific functional blocks (such as microelectromechanical systems gyroscope and accelerometer sensors, microcontroller (MCU), radio transceiver, antenna, etc.) are first assigned to each of the six faces which are each 1 cm2 in area. The FPC cross is then developed into a 1 cm3, 3D configuration by folding the cross at each of five bend planes. The result is ...

Low voltage four‐quadrant analog multiplier using dynamic threshold MOS transistors

Abstract: Purpose – Real‐time multiplication of two analog signals is one of the most important operations in analogue signal processing. Driven by low‐power and low‐voltage requirements for integrated mixedsignal portable applications, the paper's aim is to propose a novel four‐quadrant low‐voltage analog multiplier using dynamic threshold MOS transistors (DTMOS).Design/methodology/approach – The SPICE simulations were performed with 0.25 μm technology parameters and results verify the performance of the circuit. The multiplier is simulated at low‐supply voltage of ±0.5 V.Findings – The proposed multiplier has high linearity and simple structure hence it is suitable for high‐performance and low‐power analog VLSI applications.Originality/value – A new low‐voltage four quadrant analog multiplier using DTMOS circuit topology is presented in the paper.

Analysis of non‐ideal effects in coupled VLSI interconnects with active and passive load variations

Abstract: Purpose – The aim of this paper is to analyze the effects of aggressor‐line load variations (both active gate and passive capacitive loads) on the non‐ideal effects of a coupled VLSI‐interconnect system.Design/methodology/approach – Signal delay, power dissipation and crosstalk noise in interconnect can be influenced by variation in load of another interconnect which is coupled to it. For active gate and passive capacitive load variations, such effects are studied through SPICE simulations of a coupled interconnect pair in a 0.13 μm technology. Crosstalk between a coupled pair, is affected by transition time of the coupled signal, interconnect length, distance between interconnects, size of driver and receiver, pattern of input, direction of flow of signal and clock skew. In this work, influence of an aggressor‐line load variations (both active gate and passive capacitive loads) on the non‐ideal effects of delay, power consumption and crosstalk in a victim‐line of a coupled VLSI‐interconnect system are de...

Ruthenium dioxide doped manganite‐based NTC thermistors for low‐resistance applications

Abstract: Purpose – The purpose of this paper is to study the properties of disc type negative temperature coefficient (NTC) thermistors based on the spinel system Mn‐Co‐Ni‐O with the doping of RuO2 for the low‐resistance applications.Design/methodology/approach – Emphasis was placed on the properties of ruthenium dioxide doped manganite spinel system for low‐resistance applications. The properties such as microstructure, X‐ray diffraction analysis and electrical properties are reported.Findings – The prepared NTC thermistor compositions revealed the room temperature resistance and thermistor constant in the range of 28‐2,950 Ω and 1,539‐3,428 K, respectively. Hence, the prepared NTC thermistors with low resistance and moderate sensitivity are suitable from an industrial applications point of view.Originality/value – The paper reports upon a synthesis procedure which is a straightforward preparation of highly densified ternary oxide (Mn‐Co‐No‐O) thermistors.

Comparison of low cost, insulated aluminium substrates used as integrated heat sinks with conventional technology

Abstract: Purpose – The purpose of this paper is to describe two new thick film paste systems (one glass‐based and the other polymer‐based) for insulating aluminium substrates and allowing components like high‐intensity light‐emitting diodes to be attached to a conductor deposited on the dielectric.Design/methodology/approach – Comparative measurements of the thermal resistance of different substrates mounted with metal‐oxide semiconductor field‐effect transistors were made.Findings – The thermal advantages of these two technologies have been proved.Originality/value – This paper presents useful comparative data from a replicated application using different combinations of substrates. The paper shows how the superior properties of the two new systems have been proven by thermal resistance measurements. From a thermal point of view, it is only the expensive 4 W m−1 K−1 insulated metal substrate that competes with the “low cost” systems.

Electrical properties and electrical equivalent models of thick‐film and LTCC microcapacitors

Abstract: Purpose – A capacitor is a basic electronic passive component. Thick‐film technology allows manufacturing of capacitors covering the range of small and medium capacitances and they have been investigated in depth already. Low temperature co‐fired ceramics (LTCC) technology makes it possible to fabricate buried capacitors, which leads to increased packaging density, but such components’ properties are not well known. The purpose of this paper is to present the results of investigations on thick‐film and LTCC capacitors made in various technological variants.Design/methodology/approach – Thick‐film and LTCC capacitors were made in various technological variants. Different capacitor inks, metallurgy of electrodes and component constructions were investigated. Basic electrical properties and stability were determined. An electrical equivalent circuit of such components was developed based on frequency and temperature characteristics.Findings – Simple electrical equivalent circuits of self‐made thick‐film and ...

FPGA placement by using Hopfield neural network

Abstract: Purpose – The aim of this work is to examine the Hopfield network for the field programmable gate array (FPGA) cell placement.Design/methodology/approach – Implementation of an algorithm in FPGA circuits requires synthesis, placement and the routing of logic cells. The placement takes the longest time for computation. Therefore, an algorithm for a run‐time reconfigurable system can be chosen from among earlier prepared algorithms. This paper presents a Hopfield neural network for solving the placement problem. The Hopfield network was also used for processing units in a parallel placement. Hardware implementation of presented solutions could accelerate the FPGA placement by orders of magnitude in comparison with placers executed on traditional computers. Hardware accelerators could also be applied to the design of other VLSI circuits. The simulation results for the FPGA placement are presented.Findings – The Hopfield network and parallel placement give comparable placements with the method using a simulat...

A simple rail‐to‐rail CMOS voltage follower

Abstract: Purpose – The paper aims to present a simple rail‐to‐rail CMOS voltage follower.Design/methodology/approach – The circuit is developed based on a complementary source follower with a common‐source output stage. The circuit is designed using a 0.13 μm CMOS technology, and operates under the supply voltage of 1.5 V. HSPICE is used to verify the circuit performance.Findings – The simulations show output voltage swing of ±0.6 V (300 Ω load) with the total harmonic distortion of 0.55 per cent at the operating frequency of 3 MHz. The bandwidth and power dissipation are 657 MHz and 405 μW, respectively.Originality/value – A simple rail‐to‐rail CMOS voltage follower is presented.

Silicon Schottky barrier photodiodes with a thin AlN nucleation layer

Abstract: Purpose – The purpose of this paper is to present the characteristics of novel silicon Schottky barrier (SB) photodiodes (PDs) with aluminium nitride (AlN) (100 nm) nucleation layer.Design/methodology/approach – Comparison was made with conventional silicon SB PDs.Findings – It was found that smaller dark current could be achieved with AlN nucleation layer. It was also found that effective SB height increased from 0.65 to 0.71 eV with the insertion of the AlN layer. The dark leakage current for the Schottky PDs with the AlN layer was shown to be about two orders of magnitude smaller than that for the conventional silicon SB PDs.Research limitations/implications – It is possible that the detrimental effect of interface states situated near the metal semiconductor interface was less pronounced for the sample owing to the insertion of the AlN nucleation layer.Originality/value – There is believed to be no other report on silicon SB PDs capped with an AlN layer in the literature. This paper describes the fabr...

Exploiting narrow values for faster parity generation

Abstract: Purpose – The purpose of this paper is to reduce parity generation latency if the input value is narrow.Design/methodology/approach – Soft errors caused by cosmic particles and radiation emitted by the packaging are important problems in contemporary microprocessors. Parity bits are used to detect single bit errors that occur in the storage components. In order to implement parity logic, multiple levels of XOR gates are used and these XOR trees are known to have high delay. Many produced and consumed values inside a processor hold consecutive zeros and ones in their upper order bits. These values can be represented with less number of bits and hence are termed narrow. In this paper, a parity generator circuit design is proposed that is capable of generating parity if the input value is narrow. It is shown that the parity can be generated faster than a regular XOR tree implementation using this design for the values that can be represented using fewer bits.Findings – The proposed technique reduces the pari...

Application of a low‐glitch current cell in 10‐bit CMOS current‐steering DAC

Abstract: Purpose – The purpose of this paper is to describe the application of low‐glitch current cell in a digital to analog converter (DAC) to reduce the clock‐feedthrough effect and achieve a low power consumption.Design/methodology/approach – A low‐glitch current switch cell is applied in a ten‐bit two‐stage DAC which is composed of a unary cell matrix for six most significant bits and a binary weighted array for four least significant bits (LSBs). The current cell is composed of four transistors to neutralize the clock‐feedthrough effect and it enables DAC to operate in good linearity and low power consumption. The prototype DAC is being implemented in a 0.35μm complementary metal‐oxide semiconductor process. The reduction in glitch energy and power consumption has been realized by preliminary experiment and simulation.Findings – Compared to conventional current cell, more than 15 per cent reduction of glitch energy has been obtained in this work. The DAC is estimated that differential nonlinearity is within ...

VDMOSFET reliability dependence on the integrated drain‐source junction

Abstract: Purpose – This work aims to investigate the modifications in a transistor behavior after hot carrier injection processes from the integrated junction.Design/methodology/approach – A high voltage is applied across the drain‐source contacts, so a reverse current is induced through the integrated junction and defects are then created.Findings – The results point out to a dependence of the VDMOSFET reliability on the operating conditions which could induce parasitic effects on the structure. Induced defects alter the form of several MOSFET characteristics.Originality/value – A new method of degradation is presented along with a series of characterization techniques‐based electrical parameters variations.

Novel layout technique for on‐chip inductance minimization

Abstract: Purpose – The purpose of this paper is to minimize on‐chip inductance effect for modern very large‐scale integration (VLSI), ultra large‐scale integration (ULSI) systems.Design/methodology/approach – As operating frequency increases, parasitic inductance has become a major concern for electronic design on both delay and coupling noises. The impacts of on‐chip inductance are strongly associated with higher frequency operation, denser interconnect geometry, reductions of resistance, and capacitance of interconnects. The paper presents a novel layout technique – opposing inter‐digitating routing, to generate magnetic fields in opposing directions; consequently, effective magnetic field is minimized, or inductance effect is reduced. To prove the effectiveness of these approaches, 3D field solver FastHenry is used to extract inductance data and verify the results.Findings – Verification shows that this proposed method gives more than ten times reduction in self‐inductance while mutual inductance reduces even f...

Response of Ag thick film microstrip equilateral triangular patch antenna to overlay of moisture laden soybean

Abstract: Purpose – The purpose of this paper is to report on the Ku band microwave characteristics of moisture laden soya seeds using overlay technique.Design/methodology/approach – Ku band (13‐18 GHz) moisture dependent microwave permittivity, conductivity, penetration depth of moisture laden soybean (Glycine Max) using overlay on Ag thick film equilateral triangular patch antenna are studied. The change in the frequency response of the patch antenna due to change in moisture content of the soybean overlay has been used to obtain the various microwave properties.Findings – The permittivities obtained are in the range expected of moisture laden soybean. As moisture content increases microwave dielectric constant, dielectric loss, and conductivity of soybean increases. Only the amplitude data have been used here.Originality/value – Ku band characterization of soybean has been done using overlay technique. The thick film patch antenna is sensitive even to ∼4 percent moisture content in the overlay material. This can...

Comparison between models for p‐n junctions parameters extraction

Abstract: Purpose – The purpose of this paper is to compare different junctions' parameters extraction models.Design/methodology/approach – I‐V curves of p+‐n and pwell‐n diodes were measured. Five models for parameters extraction on I‐V characteristics of diodes in an educational poly‐Si gate pwell complementary metal oxide semiconductor (CMOS) technology were applied. The junctions' areas were 30 × 30 μm for the source‐body p+‐n junction of the PMOS transistor and 220 × 250 μm for the pwell‐body junction. The diodes were sintered in forming gas (10 percent of H2) in the temperature interval of 450‐525°C for times from 30 min up to 4 h.Findings – It was shown that the best annealing regimes are different for both kinds of junctions.Originality/value – The paper shows that the best annealing regime for p+‐n diodes (the lowest n and I0 values) is 450°C, 30 min and for the pwell‐n diodes (the lowest I0 values) is 525°C, 60 min. So, for the different kinds of junctions in one integrated circuit, different annealings c...