Showing papers in "Microprocessing and Microprogramming in 1991"

TL;DR: A heuristic method is presented for suboptimal multiple-objective sequential general decomposition of sequential machines into submachines with limited input/output bits, product terms and state variables and shows that it is efficient and flexible.

TL;DR: The results of a systematic study conducted to evaluate the influence of layout and design methodologies on the performance of basic computation primitives in DSP and image processing systems are presented.

TL;DR: A family of algorithms for deriving protocol specifications from service specifications has been developed by Bochmann et al., the algorithms accept an arbitrary number of protocol entities, communicating over reliable FIFO channels.

TL;DR: Analyzes some features of the Helios distributed operating system to valuation the available facilities under Helios and estimates the development interface of Helios, the possibilities of message-passing, the questions of communication reliability and the interest of the notion of task.

TL;DR: A shared memory architecture for parallel cyclic reference counting as an alternative to mark-scan based architectures is presented.

TL;DR: A high-speed machine vision system that has been designed for real-time automatic inspection and qualification of “row” and “uni” textile materials and attention is directed to hardware development and construction using high speed image processing and algorithm-oriented circuits.

TL;DR: Two PLA-based microcontrol architectures are proposed that are suitable for modular microprogramming and an bit-slice approach is taken in the second scheme which allows for easy microcontrol expandability and compaction of the sequence store.

TL;DR: Design and implementation of a hierarchical real-time expert-system architecture directed to real- time diagnosis of modern production systems and results about the system behaviour are shown by means of a graphical user interface based on X Window/Motif.

TL;DR: This paper presents a method of computing testability with reconvergent fanout checking and redundant fault detecting, while keeping a reasonable computation complexity.

TL;DR: Assessment of the suitability of two techniques, based on Petri nets and temporal logic, for the specification, design and verification of a real-time industrial control system that forms part of a high speed packaging machine shows that the problem can be specified elegantly and the verification can be completely carried out using temporal logic.

TL;DR: The enhancement of the term “object oriented” is explained in this paper and a new approach is introduced for the structured analysis of data processing systems.

TL;DR: A methodology for distinguishing the phases of the software life cycle is introduced and makes it possible to support support phase-specific measures and planning activities during the service life of the system.

TL;DR: An efficient recovery scheme for nested transactions using double log sequence numbers (LSNs) is proposed, which is able to avoid unnecessary redos and subsequent undos and can cope with successive crashes which might occur during recovery.

TL;DR: A synthesizable VHDL subset is defined with constructs focusing on synchronization and communication with new object types representing mutual exclusion data, communication data and events.

TL;DR: An integrated simulation environment for the design and evaluation of parallel computing systems is presented, designed for a large-grain data flow programming model, which is called Weighted Behavioral Graph (WBG).

TL;DR: A polynomial-time Occam program for automatically mapping parallel programs onto multiprocessor systems based on the heuristic strategy of self-adjusting mapping, which works very well and produces satisfactory results for both regular and irregular task graphs.

TL;DR: It is shown that with careful network design, the backpropagation learning procedure is an effective way of training neural networks for histological image understanding and it is demonstrated that symmetric functions yield faster convergence and 100% generalisation performance.

TL;DR: GM-C is an abstract machine for the compilation of lazy functional languages based on Categorical Multi-Combinators and is inspired by Johnsson’s G-Machine.

TL;DR: Preliminary results for complexity evaluation of alternative architectures related to architectural synthesis start from the definition of the formalism, based on Data Flow Graph (DFG), adopted for higher level synthesis of alternative complex architectures.

TL;DR: Two algorithms for dynamic load balancing in a distributed computer system to try to reduce the difference of workload amongst processors are presented.

TL;DR: The criteria for path-disjoint routing is studied, heuristic approaches to the criteria are given, and a fast heuristic algorithm is presented to solve this problem in transputer networks.

TL;DR: A system which not only integrates design/synthesis with formal verification but also addresses the crucial issue of how such tools are to be accessible to design engineers.

TL;DR: A number of problems are pointed out, which require an extension of the conversation scheme and the integration with other fault tolerance mechanisms, in order to reach a higher degree of reliability.

TL;DR: This paper presents a conceptual and formal model for the definition of visual languages and this model is then used to define an aspect of language support environments, namely a language-directed editing facility.

TL;DR: An efficient combination of switch level and gate level test generation providing robust 2-pattern pairs via dynamic coupling of test generators providing high fault coverage for non-trivial faults in CMOS circuits is described.

TL;DR: This paper presents a method for synthesizing a data path from a simple description of the instruction set of an application specific processor which can be programmed in the programming language C.

TL;DR: The described mechanism subdivides the controller of each SIMD machine in two levels, spliting thus the problems of accesses to the data and the management of communications, and uses floating channel objects implemented in the shared memory.

TL;DR: The behavioral specifications are given in an extended version of Prolog that allows the high-level description of algorithms to be implemented in special-purpose VLSI circuits, allowing the implementation of fast special- Purpose architectures for a wide range of practical computing problems.

TL;DR: A methodology for transformational design and implementation of embedded software, which is based on an original extension to Petri nets, which provides a framework for creating an executable specification, automated transformation of the specification structure, simulated execution, and validation of the specifications behavior.

TL;DR: A C++ interface to the STM which provides stable classes is defined which can be used to write robust object oriented programs which resist processor failures using stable objects and transactions.