Journal ArticleDOI
A New Simultaneous Multislope ADC Architecture for Array Implementations
TLDR
A new simultaneous multislope analog-digital converter architecture suitable for array implementations in, e.g., CMOS image sensors (CISs), which is almost twice as fast as a conventional-slope ADC, while it requires only a small amount of extra circuitry.Abstract:
This brief presents a new simultaneous multislope analog-digital converter (ADC) architecture suitable for array implementations in, e.g., CMOS image sensors (CISs). The simplest implementation is almost twice as fast as a conventional-slope ADC, while it requires only a small amount of extra circuitry. Measurements have been performed on a custom made CIS which implements parts of the proposed ADC. The measurements show good linearity and verify the concept of the new architectureread more
Citations
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Journal ArticleDOI
Multiple-Ramp Column-Parallel ADC Architectures for CMOS Image Sensors
TL;DR: A CMOS imager with a column-parallel ADC architecture based on a multiple-ramp single-slope (MRSS) ADC that can be easily adapted to exhibit a companding characteristic, which exploits the amplitude-dependent nature of the photon shot noise present in imager signals.
Journal ArticleDOI
A High-Speed CMOS Image Sensor With Column-Parallel Two-Step Single-Slope ADCs
TL;DR: A column-parallel two-step single-slope (SS) ADC for high-speed CMOS image sensors and error correction scheme to improve the linearity is proposed.
Journal ArticleDOI
Noise Analysis and Simulation Method for a Single-Slope ADC With CDS in a CMOS Image Sensor
Jimin Cheon,Gunhee Han +1 more
TL;DR: This paper presents a noise estimation method for the CDS/SS-ADC that uses the FNS results while the transient noise behavior is taken into account, and provides noise estimation results closer to that of the TNS than the conventional FNS.
Journal ArticleDOI
High Frame-Rate VGA CMOS Image Sensor Using Non-Memory Capacitor Two-Step Single-Slope ADCs
TL;DR: This paper proposes a column-parallel two-step single-slope analog-to-digital converter (SS ADC) for high-frame-rate CMOS image sensors and employs redundancy error correction logic to calibrate the error between the coarse and fine steps.
Journal ArticleDOI
8.3 M-Pixel 480-fps Global-Shutter CMOS Image Sensor with Gain-Adaptive Column ADCs and Chip-on-Chip Stacked Integration
Yusuke Oike,Kentaro Akiyama,Luong D. Hung,Wataru Niitsuma,Akihiko Kato,Mamoru Sato,Yuri Kato,Wataru Nakamura,Hiroshi Shiroshita,Yorito Sakano,Yoshiaki Kitano,Takuya Nakamura,Takayuki Toyama,Hayato Iwamoto,Takayuki Ezaki +14 more
TL;DR: This paper presents a 4K2K 480-fps global-shutter CMOS image sensor with a super 35-mm format for a highly realistic digital video system and employs newly developed gain-adaptive column analog-to-digital converters.
References
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A 256/spl times/256 CMOS imaging array with wide dynamic range pixels and column-parallel digital output
TL;DR: A 256x256 CMOS active pixel sensor (APS) is described for an automotive stereo-vision system that simultaneously provides flexibility, user-adjustability, and digital control, with no reduction of fill factor.
Proceedings ArticleDOI
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Tadashi Sugiki,Shinji Ohsawa,Hiroki Miura,Michio Sasaki,Nobuo Nakamura,I. Inoue,M. Hoshino,Y. Tomizawa,T. Arakawa +8 more
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Journal ArticleDOI
A high-speed, 240-frames/s, 4.1-Mpixel CMOS sensor
TL;DR: In this paper, a large-format 4-Mpixel (2352/spl times/1728) sensor with on-chip parallel 10-b ADCs is described, achieving a high frame rate of 240 frames/s delivering 9.75 Gb/s of data with power dissipation of less than 700 mW.
Journal ArticleDOI
A 9-V/Lux-s 5000-frames/s 512/spl times/512 CMOS sensor
Alexander Krymski,Nianrong Tu +1 more
TL;DR: A comparison between two high-speed digital CMOS sensor architectures, which are a column-parallel APS and a digital pixel sensor (DPS), is conducted.
Proceedings ArticleDOI
An integrated 800/spl times/600 CMOS imaging system
TL;DR: In this article, a single chip digital CMOS imaging system with SVGA pixel array, linear bank of 800 parallel 8 b ADCs, 3.2 kB DRAM buffer, digital double sampling (DDS) circuitry and digital control is presented.