Proceedings ArticleDOI
A CMOS Image Sensor with Focal Plane Discrete Cosine Transform Computation
Edwin J. Tan,Zeljko Ignjatovic,Mark F. Bocko +2 more
- pp 2395-2398
TLDR
An image sensor with nonuniform pixel placement that enables a highly efficient computation of the discrete cosine transform, which is the most computationally demanding step of the image compression algorithm.Abstract:
In this paper we describe an image sensor with nonuniform pixel placement that enables a highly efficient computation of the discrete cosine transform, which is the most computationally demanding step of the image compression algorithm. This technique is based on the arithmetic Fourier transform (AFT), which we show to be 5 times more computationally efficient than currently used DCT computation methods. The architecture and circuits described can be implemented in conventional CMOS processes.read more
Citations
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Journal ArticleDOI
The Arithmetic Cosine Transform: Exact and Approximate Algorithms
TL;DR: The central mathematical properties of the ACT are provided, necessary in designing efficient and accurate implementations of the new transform method, the arithmetic cosine transform (ACT), which is introduced in this paper.
Journal ArticleDOI
Contribution to the design of a CMOS image sensor with low-complexity video compression for wireless sensor networks
TL;DR: A smart image sensor integrating a user-driven video compression scheme designed to respect the energy constraints of image processing and transmission over WSNs is presented and its performance is described.
Dissertation
Conception d'un micro capteur d'image CMOS à faible consommation d'énergie pour les réseaux de capteurs sans fil
TL;DR: De par sa nature, une application multimedia impose un traitement intensif au niveau du noeud and un nombre considerable de paquets a echanger a travers le lien radio, and par consequent beaucoup d'energie a consommer.
Journal ArticleDOI
VLSI Computational Architectures for the Arithmetic Cosine Transform
TL;DR: A hardware architecture for the computation of the null mean ACT is proposed, followed by a novel architectures that extend the ACT for non-null mean signals, utilizing the novel architecture described.
Journal ArticleDOI
VLSI Computational Architectures for the Arithmetic Cosine Transform
TL;DR: In this article, a hardware architecture for the computation of the null mean ACT is proposed, followed by a novel architectures that extend the ACT for non-null mean signals. All circuits are physically implemented and tested using the Xilinx XC6VLX240T FPGA device and synthesized for 45 nm TSMC standard-cell library for performance assessment.
References
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Journal ArticleDOI
A Fast Computational Algorithm for the Discrete Cosine Transform
TL;DR: A Fast Discrete Cosine Transform algorithm has been developed which provides a factor of six improvement in computational complexity when compared to conventional DiscreteCosine Transform algorithms using the Fast Fourier Transform.
Journal ArticleDOI
On the Computation of the Discrete Cosine Transform
M.J. Narasimha,A. Peterson +1 more
TL;DR: An N -point discrete Fourier transform (DFT) algorithm can be used to evaluate a discrete cosine transform by a simple rearrangement of the input data.
Journal ArticleDOI
New fast recursive algorithms for the computation of discrete cosine and sine transforms
Zoran Cvetkovic,Miodrag Popovic +1 more
TL;DR: Fast recursive algorithms for the computation of the discrete cosine and sine transforms are developed, which have less multiplications by two, and add operations are better positioned, giving rise to faster computation and easier VLSI implementation.
Proceedings ArticleDOI
A 80 /spl mu/W/frame 104/spl times/128 CMOS imager front end for JPEG compression
TL;DR: A programmable 80 /spl mu/W/frame (3.3 V supply) single-chip architecture that combines a CMOS imager and an analog image processor capable of computing separable block matrix transforms (DCT, Haar, etc) is presented.
Proceedings ArticleDOI
Arithmetic Fourier Transform And Adaptive Delta Modulation: A Symbiosis For High Speed Computation
D W. Tufts,G Sadasiv +1 more
TL;DR: Motivated by the goal of efficient, effective, high-speed realization of the algorithm in an integrated circuit, this work introduces further simplicities by the use of delta modulation to represent the input function in digital form.