Proceedings ArticleDOI
A hierarchical methodology to improve channel routing by pin permutation
C.Y. Hou,C.Y.R. Chen +1 more
- pp 440-443
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TLDR
A hierarchical pin permutation algorithm is presented which is used as a preprocessor of conventional channel routing algorithms such that the results of the subsequent channel routing can be significantly improved.Abstract:
A hierarchical pin permutation algorithm is presented which is used as a preprocessor of conventional channel routing algorithms. This algorithm determines the proper positions of permutable gates and cell terminals such that the results of the subsequent channel routing can be significantly improved. First, gates and terminals are interchanged to maximize the number of aligned terminal pairs and to reduce the channel density. Then, terminals that are not aligned are interchanged to remove cyclic constraints in the vertical constraint graph (VCG). Experimental results show that the proposed algorithm considerably reduces the number of tracks and vias. >read more
Citations
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Proceedings ArticleDOI
Effects of transistor reordering on the performance of MOS digital circuits
B.S. Carlson,C.Y.R. Chen +1 more
TL;DR: The investigation shows that the effect of transistor reordering on the timing performance of a MOS logic gate varies significantly depending on transistor strengths, stack height, load capacitance and critical input signal transition time.
Patent
Efficient routing of conductors between datapaths
TL;DR: In this paper, a method for routing conductive paths between a first datapaths and a second datapath in an integrated circuit is described, where the least aligned block pair to be routed is chosen from block one and block N, and the remaining unrouted block pairs are chosen to be the block pair immediately adjacent to the most recently routed block pair.
Proceedings ArticleDOI
Channel density minimization by pin permutation
TL;DR: The present algorithm has important applications in hierarchical layout design of integrated circuits and it is shown that the problem of minimizing wire length by permuting terminals is NP-hard in the strong sense.
Journal ArticleDOI
River routing and density minimization for channels with interchangeable terminals
TL;DR: A linear-time algorithm is presented that detects whether there exists an interchange of the terminals that can lead to a river routable channel, and if so, how to find an interchange that minimizes the density of the channel.
Proceedings ArticleDOI
Timing-driven pin assignment with improvement of cell placement in standard cell layout
Shin'ichi Wakabayashi,T. Koide +1 more
TL;DR: In this paper, a timing-driven pin assignment algorithm with improvement of cell placement in standard cell layout is proposed to minimize the channel density as well as the total wire length by assigning nets to pins of cells under the given timing constraints.
References
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Proceedings ArticleDOI
Wire routing by optimizing channel assignment within large apertures
TL;DR: The purpose of this paper is to introduce a new wire routing method for two layer printed circuit boards based on the newly developed channel assignment algorithm and requires many via holes.
Journal ArticleDOI
Efficient Algorithms for Channel Routing
Takeshi Yoshimura,Ernest S. Kuh +1 more
TL;DR: Two new algorithms merge nets instead of assigning horizontal tracks to individual nets to route a specified net list between two rows of terminals across a two-layer channel in the layout design of LSI chips.
Proceedings ArticleDOI
A “DOGLEG” channel router
TL;DR: The routing algorithm presented here was developed as part of LTX, a computer-aided design system for integrated circuit layout and was implemented on an HP-2100 minicomputer.