Proceedings ArticleDOI
A high-throughput cost-effective ASIC implementation of the AES Algorithm
Qingfu Cao,Shuguo Li +1 more
- pp 805-808
TLDR
A novel on-the-fly key expansion structure is applied to improve the throughput and outperforms prior works with respect to the parameter throughput per kilo gates with the same process1.Abstract:
This paper proposes a high-throughput cost-effective implementation of AES supporting encryption and decryption with 128-, 192-, and 256-bit cipher key. Optimum irreducible polynomial coefficients are selected to construct the composite field GF(((22)2)2) on standard and normal base in order to minimize the gate count in SubBytes/InvSubBytes transformation. In addition, MixCoulmn/InvMixColumn transformations are optimized and the gate count is the least as we know. And then, a novel on-the-fly key expansion structure is applied to improve the throughput. The performance is evaluated on SMIC 0.18µm CMOS technology and the design has been verified on FPGA. The throughput can achieve at 1.16Gbps with the cost of only 19476 equivalent NAND2 gates, which outperforms prior works with respect to the parameter throughput per kilo gates with the same process1.read more
Citations
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Proceedings ArticleDOI
AES-512: 512-bit Advanced Encryption Standard algorithm design and evaluation
TL;DR: An FPGA architecture for a new version of the Advanced Encryption Standard (AES) algorithm that uses input block size and key size of 512-bits which makes it more resistant to cryptanalysis with tolerated area increase is presented.
Proceedings ArticleDOI
A combinational logic implementation of S-box of AES
TL;DR: This paper presents a combinational logic based Rijndael S-box implementation for the SubByte transformation on ASIC that results in low cost, small area occupancy and high throughput as compared to the typical ROM based lookup table implementation with fixed and unbreakable access time.
Journal ArticleDOI
Iterative and Fully Pipelined High Throughput Efficient Architectures of AES in FPGA and ASIC
TL;DR: A logical rearrangement has been performed in the byte substitution (S-box) module to reduce the number of gates in the critical path and inversion in GF(24) module has been separately optimized.
Journal ArticleDOI
A Robust Fault Detection Scheme for the Advanced Encryption Standard
TL;DR: A fault detection scheme for the Advanced Encryption Standard and its details implementation in each transformation of the AES is presented, and the simulation results show that the fault coverage achieves 99.999% for the proposed scheme.
Proceedings ArticleDOI
ASIC implementation of AES
TL;DR: A low power implementation of rolled architecture for AES encryption and decryption with a very low power consumption of 22.85mW is proposed.
References
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Book ChapterDOI
A Compact Rijndael Hardware Architecture with S-Box Optimization
TL;DR: Compact and high-speed hardware architectures and logic optimization methods for the AES algorithm Rijndael are described, including a new composite field and the S-Box structure is also optimized.
Book ChapterDOI
A very compact s-box for AES
TL;DR: This work refines the most compact implementations of AES by examining many choices of basis for each subfield, not only polynomial bases as in previous work, but also normal bases, giving 432 cases to achieve a more compact S-box.
Journal ArticleDOI
High-speed VLSI architectures for the AES algorithm
Xinmiao Zhang,Keshab K. Parhi +1 more
TL;DR: Using the proposed architecture, a fully subpipelined encryptor with 7 substages in each round unit can achieve a throughput of 21.56 Gbps on a Xilinx XCV1000 e-8 bg560 device in non-feedback modes, which is faster and 79% more efficient in terms of equivalent throughput/slice than the fastest previous FPGA implementation known to date.
Journal Article
A very compact S-box for AES
TL;DR: In this paper, the S-box size was reduced to 4 bits and 2 bits by using polynomial bases for each subfield and normal bases for all subfields, and the isomorphism bit matrices were fully optimized, improving the greedy algorithm.
Book ChapterDOI
An ASIC Implementation of the AES SBoxes
TL;DR: This article presents a hardware implementation of the S-Boxes from the Advanced Encryption Standard (AES), and shows that a calculation of this function and its inverse can be done efficiently with combinational logic.