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Proceedings ArticleDOI

A machine learning-based approach for thread mapping on transactional memory applications

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TLDR
This paper proposes a machine learning-based approach to automatically infer a suitable thread mapping strategy for transactional memory applications and shows that this approach improves performance up to 18.46% compared to the worst case and up to 6.37% over the Linux defaultthread mapping strategy.
Abstract
Thread mapping has been extensively used as a technique to efficiently exploit memory hierarchy on modern chip-multiprocessors. It places threads on cores in order to amortize memory latency and/or to reduce memory contention. However, efficient thread mapping relies upon matching application behavior with system characteristics. Particularly, Software Transactional Memory (STM) applications introduce another dimension due to its runtime system support. Existing STM systems implement several conflict detection and resolution mechanisms, which leads STM applications to behave differently for each combination of these mechanisms. In this paper we propose a machine learning-based approach to automatically infer a suitable thread mapping strategy for transactional memory applications. First, we profile several STM applications from the STAMP benchmark suite considering application, STM system and platform features to build a set of input instances. Then, such data feeds a machine learning algorithm, which produces a decision tree able to predict the most suitable thread mapping strategy for new unobserved instances. Results show that our approach improves performance up to 18.46% compared to the worst case and up to 6.37% over the Linux default thread mapping strategy.

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Citations
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Machine Learning-Based Self-Adjusting Concurrency in Software Transactional Memory Systems

TL;DR: A machine-learning based approach is proposed which enables STM systems to predict their performance as a function of the number of concurrent threads in order to dynamically select the optimal concurrency level during the whole lifetime of the application.
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Using meta-heuristics and machine learning for software optimization of parallel computing systems : a systematic literature review

TL;DR: While modern parallel computing systems offer high performance, utilizing these powerful computing resources to the highest possible extent demands advanced knowledge of various hardware architectu... as discussed by the authors, which requires advanced knowledge from various hardware architectures.
Proceedings ArticleDOI

Compiler support for selective page migration in NUMA architectures

TL;DR: This paper proposes compiler analyses and code generation methods to support a lightweight runtime system that dynamically migrates memory pages to improve data locality and compares the approach against Minas, a middleware that supports NUMA-aware data allocation, and shows that it can outperform it by up to 50% in some cases.
References
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Journal ArticleDOI

Induction of Decision Trees

J. R. Quinlan
- 25 Mar 1986 - 
TL;DR: In this paper, an approach to synthesizing decision trees that has been used in a variety of systems, and it describes one such system, ID3, in detail, is described, and a reported shortcoming of the basic algorithm is discussed.
Journal ArticleDOI

Neural networks for classification: a survey

TL;DR: The issues of posterior probability estimation, the link between neural and conventional classifiers, learning and generalization tradeoff in classification, the feature variable selection, as well as the effect of misclassification costs are examined.
Proceedings ArticleDOI

STAMP: Stanford Transactional Applications for Multi-Processing

TL;DR: This paper introduces the Stanford Transactional Application for Multi-Processing (STAMP), a comprehensive benchmark suite for evaluating TM systems and uses the suite to evaluate six different TM systems, identify their shortcomings, and motivate further research on their performance characteristics.
Journal Article

Transactional locking II

TL;DR: This paper introduces the transactional locking II (TL2) algorithm, a software transactional memory (STM) algorithm based on a combination of commit-time locking and a novel global version-clock based validation technique, which is ten-fold faster than a single lock.
Book ChapterDOI

Transactional locking II

TL;DR: TL2 as mentioned in this paper is a software transactional memory (STM) algorithm based on a combination of commit-time locking and a novel global version-clock based validation technique, which is ten times faster than a single lock.