A
Multilevel Voltage-Source Inverter with Separate
DC
Sources
for
Static Var Generation
Fang
Zheng Peng
University of Tennessee, Knoxville
Oak Ridge National Laboratory
Oak
Ridge, Tennessee 37831-7258
Phone: 615-576-7261
P.O. BOX
2003,
K-l008F,
M/S
7258
Abstract
-
A
new multilevel voltage-source inverter with
separate dc sources is proposed for high-voltage, high-power
applications, such
as
flexible ac transmission systems
(FACTS)
including static var generation
(SVG),
power line conditioning,
series compensation, phase shifting, voltage balancing, fuel cell
and photovoltaic utility systems interfacing, etc. The new
M-level inverter consists
of
(M-1)/2
single phase full bridges
in
which each bridge has its own separate dc source.
This
inverter
can generate
almost
sinusoidal waveform voltage with only one
time switching per cycle
as
the number of levels increases. It
can
solve the problems
of
conventional transformer-based multipulse
inverters and the problems of the multilevel diode-clamped
inverter and the multilevel flying capacitor inverter.
To
demonstrate the superiority of the new inverter, a
SVG
system
using the new inverter topology is discussed through analysis,
simulation and experiment.
I.
INTRODUCTION
A.
Background
With long-distance ac power transmission and load
growth, active control of reactive power (var) is indispensable
to stabilize the power systems and to maintain the supply
voltage. Static Var Generators (SVGs) using voltage-source
inverters have been widely accepted
as
the next generation
reactive power controllers of power systems to replace the
conventional var compensators, such as Thyristor Switched
Capacitors
(TSCs)
and Thyristor Controlled Reactors (TCRs)
Fig.
1
shows a typical 48-pulse inverter for static var
generation applications. The 48-pulse inverter consists of
eight 6-pulse inverters connected together through eight
zigzag-connection or WyeDelta and DeltaDelta connection
transformers, in order to reduce harmonic distortion using the
harmonic neutralization (cancellation) technique
[
1,
21.
These transformers, which are also called harmonic
neutralizing magnetics,
[I-51.
Jih-Sheng
Lai,
John McKeever
and
James VanCoevering
Oak
Ridge National Laboratory*
Oak
Ridge, Tennessee 37831-7258
Phone: 615-576-6223
P.O.
BOX
2003,
K-l008F,
M/S
7258
(1) are the most expensive equipment in the system,
(2) produce about
50%
of the total losses of the system,
(3)
occupy up to 40% of the total system's real estate, which
is an excessively large area,
(4)
cause difficulties in control due to DC magnetizing and
surge overvoltage problems resulting
from
saturation
of
the transformers in transient states.
To solve these problems,
a
diode-clamped multilevel inverter
and a flying-capacitor multilevel inverter have been proposed
for SVG applications [6,7,
9,
121. These multilevel inverters
can eliminate the transformers required in an
SVG
using
conventional 6-pulse inverters; however, they encounter new
problems.
B.
Multilevel Inverters and Their Problems
In
recent years, a relatively new type of inverters,
multilevel voltage source inverters, has attracted many
researchers' attention. Multilevel inverters can reach high
voltage and reduce harmonics by their own structures without
transformers, a benefit that many contributors have been
trying to appropriate for high-voltage, high-power
applications.
Fig. 2 shows the structure of a 5-level diode-clamped
inverter. This inverter can reach high performance without
transformers. It does, however, require additional clamping
diodes. For this 5-level inverter, obviously,
DI,
02,
and
03
need to block
IV,,
2V,,
and
3V,,
respectively, assuming
each dc capacitor has the same dc voltage,
V,.
When diodes
are selected to have the same voltage rating as the main
switching devices,
02
and
03
comprise two diodes in series
and three diodes in series, respectively, to withstand the
voltage. Therefore, the number of the additional clamping
diodes is equal to (M-l)*(M-2)*3 for an M-level inverter.
For example, if
M=51
(for direct connection to 69 kV power
*
Prepared by
the
Oak
Ridge National Laboratory,
Oak
Ridge, Tennessee 37831-7280, managed by Lockheed Martin
Energy
Systems, Inc.
for
the
U.
S.
Department
of
Energy under contract DE-AC05-840R21400.
The submitted manuscript has been authored by
a
contractor
of
the
U.
S.
Government under contract
No.
DE-AC05-840R21400. Accordingly, the
U.
S.
Government retains
a
nonexclusive, royalty-free license
to
publish
or
reproduce the published
form
of
this contribution,
or
allow others
to
do
SO,
for
U.
S.
Government purposes.
DISCLAIMER
Portions
of
this document may be illegible
in
electronic image products. Images
are
produced from the best available original
document.
2 of
8
lines) then the number of the clamping diodes will be 7350.
These clamping diodes not only raise costs but also cause
packaging problems and exhibit parasitic inductances; thus,
the number of levels for a multilevel diode-clamped inverter
may be limited to seven or nine in practical use
[7,
121.
Fig.
1.
Structure
of
the
conventional 48-pulse inverter.
Fig.
2.
Structure
of
the 5-level diode clamped inverter.
4
vak
A
relatively new structure, the multilevel flying-capacitor
inverter
[9],
is supposed to be able to solve the voltage
unbalance problem
[7,
131 and excessive diode count in
multilevel diode clamped inverters. Fig.
3
shows the
configuration of a 5-level flying-capacitor inverter. In this
inverter, however, a large number of flying capacitors are
needed. The required number
of
flying capacitors for an
M-level inverter, provided that the voltage rating
of each
capacitor used is the same
as
the main power switches, is
determined by the formula, (M-l)*(M-2)*3/2+(M-1). With
the assumption of the same capacitor voltage rating, an M-
level diode clamped inverter only requires
(M-1)
capacitors.
Therefore, the flying capacitor inverter requires large
capacitance compared with the conventional inverterrg]. In
addition, control is very complicated, and higher switching
frequency is required to balance each capacitor voltage[ 131.
A new multilevel inverter is proposed to solve all these
problems of the conventional multipulse and multilevel
inverters. The new multilevel inverter eliminates the
excessively large number
of
(1)
bulky transformers required
by conventional multipulse inverters,
(2)
clamping diodes
required by multilevel diode-clamped inverters, and (3) flying
capacitors required by multilevel flying-capacitor inverters.
Also, it has the following features:
1. It is much more suitable to high-voltage, high-power
applications than the conventional inverters.
2.
It switches each device only once per line cycle and
generates a multistep staircase voltage waveform
approaching a pure sinusoidal output voltage by increasing
the number of levels.
3. Since the inverter structure itself consists of a cascade
connection of many single-phase, full-bridge inverter
(FBI) units and each bridge is fed with a separate
DC
source, it does not require voltage balance (sharing)
circuits or voltage matching of the switching devices.
4.
PackagingAayout is much easier because of the simplicity
of structure and lower component count.
I
I
I
T
Fig.
3.
Structure
of
the 5-level flying capacitor inverter.
3
of
8
II.
A
NEW MULTILEVEL
INVERTER
A.
Inverter Structure and Operating Principle
Fig.
4
shows the single-phase configuration of the
proposed multilevel separate dc-source inverter. It consists of
(M-l)n
single-phase
FBI
units connected in cascade to
generate an
M
level output voltage over half fundamental
cycle. Each full-bridge inverter has its own dc source. This
new inverter, hereafter called a cascade inverter, does not
require any transformers, clamping diodes, or flying
capacitors, which are required in today's multilevel inverters.
Figs.
5
and 6 show three-phase structures of the proposed
cascade inverter (level number
M=9).
Fig.
5
is used as
an
example
to
explain its operating principle. Fig.
7
shows
waveforms generated by the 9-level cascade inverter shown in
Fig.
5.
The output phase voltage is the sum
of
four inverter
units' outputs. That is,
vCUn
=
veal
+
vca2
+
vca3
+
vca4.
Each
FBI
unit can generate three-level output,
+Vkr
0,
and
-Vk.
This is made possible by connecting the dc-source
sequentially to the ac side via the four switching devices.
Note that each device is switched only once per line cycle.
Since the phase current,
ica
,
is leading or lagging the
phase voltage
vCUn
by
90
degrees, the average charge to each
dc capacitor is equal
to
zero over every half line cycle. From
Fig.
7,
the average charge to each dc capacitor over half cycle
[0,
n],
Qi,
can be expressed
as
(1)
where,
i
=
1
-
4;
[e,
x-0J
represents the time interval during
which the dc capacitor connects to the ac side, and
I
is the
rms
value
of
the line current. Because of this symmetric
charge flow, voltages on all the dc capacitors remain
theoretically balanced.
=-%
8,
ei
=
jJZzCOSede
=
0,
Fig.
4.
Single phase structure of multilevel cascade inverter
Fig.
5.
Three phase Wye-connection structure
of
9-level cascade inverter.
Fig.
6.
Three
phase Delta-connection structure
of
9-level cascade inverter.
VCd
y,iI
I
n-8,
Fig.
7.
Waveforms of the 9-level cascade inverter shown in Fig.
5.
B.
System Configuration and Control Scheme
of
SVGs
Fig.
8
shows the system configuration and control block
diagram of an
SVG
using the new cascade inverter, where
vs
represents the source voltage,
Ls
is the source impedance, and
LC
is the inverter interface inductance. The switching pattern
table shown in Fig.
8
contains switching timings for the
inverter to generate the desired output voltage
as
shown in
Fig.
7.
The switching angles,
8,
(i=l,
2,
-,
(M-l)L’),
are
calculated off-line to minimize harmonics for each
modulation index
(MI),
which is defined as
VC*/Vcm,
where
V,’
is the amplitude command of the inverter output phase
voltage, and
VCm
is the maximum obtainable amplitude, i.e.,
the amplitude of the phase voltage when all the switching
angles,
e,,
are equal to zero.
As
mentioned in Section
II.A,
the average charge on each dc capacitor will be zero if each
FBI unit’s output voltage,
vci, lags
or
leads the line current,
ic,
by exactly
90
degrees as shown in Fig.
7,
which means that
no
real power flows into the dc capacitor; however, with no
power delivered to the dc capacitors, the dc capacitor voltage
cannot be maintained due to switching device loss and
capacitor loss. Therefore, the inverter should be controlled
so
that some real power is delivered to the dc capacitors. In
principle, each dc capacitor voltage can be controlled to be
exactly the dc command voltage,
V,*.
The control block
diagram shown in Fig.
8
includes two control loops. The
outer loop controls the total power flow to all the FBI units,
whereas the inner loop offsets power flow into each
individual unit. The control principle can be explained with
the aid of Fig.
9.
In
Fig.
9,
vs
is the source voltage,
ic
is the
current flowing into the inverter, and
vc
is the inverter output
voltage. If
vc
is controlled
so
that it lags
vs
by
a,,
then the
total real power,
P,,
flowing into the inverter is
VsVc
sina,
(2)
where
X,
is the impedance of interface inductor. Since
inverter devices
are
not ideal and have different tolerance
errors, each dc capacitor voltage may not be exactly balanced
with the outer loop only. If the ith
FBI
unit’s output voltage,
vci,
is
as
shown with the light wider line in Fig.
9,
then the
average charge into the dc capacitor over each half cycle,
the
area shown by the lighter shadow, will be almost zero.
However, if
vcl,
is shifted ahead by
Aa,,
as
shown by the
darker line waveform
in
the figure, then the charge shown by
the darker area can be expressed as
Q,
=
J&ZcosBdB
=
2fiZcos6, sin Aa,,
(3)
which is proportional to
Aa0
when
Aac,
is small. Therefore,
each FBI unit’s dc voltage can be controlled by slightly
shifting the switching pattern. The magnitude of this shift is
usually much smaller than
aC.
For
high voltage high power
applications, the total power loss
of
the inverter is typically
less than
1%,
thus
Aacle ac<O.O1 rad.
I:=
x,
%-e,
-An
cz
e,-Aa
c,
4 of
8
Mu1
tilevel
Cascade
AAA
sa
sb
sc
I,*
[varl
output
voltage
Calculation
of
Vca
+
reference of
+
Switching
-
Pattern
-
Y
T
Fig.
8.
System configuration
of
an
SVG
using the cascade inverter.
Fig.
9.
Control
principle
of
each dc capacitor voltage.
HI.
REQUIRED
CAPACITANCE
OF
DC
CAPACITORS
The above description has shown that the proposed
cascade inverter has the simplest structure and least
components, compared with the conventional multipulse
inverter, the diode-clamped multilevel inverter, and the flying
capacitor multilevel inverter. However, the new inverter’s
capacitor requirements are higher than the conventional
multipulse inverter and the diode-clamped multilevel inverter.
Here, the required capacitance of the cascade inverter will be
formulated and compared with that of the conventional
multipulse inverter.
A.
For the Conventional Multipulse Inverters
It is generally required that an
SVG
has the capability to
generate
100%
negative-sequence var for unbalanced loads or
in case of phase fault. Therefore, the required capacitance,
Cdc,
of dc capacitors used
in
the conventional inverter shown
in Fig.
1
should accommodate this generation of 100%
negative-sequence var and can be expressed
as