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Journal ArticleDOI

A new approach to topological via minimization

TLDR
A two-chain maximum dominance problem, which is of interest in its own right, is considered, and its applications to other very large-scale integration layout problems are shown.
Abstract
A topological via minimization problem in a two-layer routing environment is examined. The problem of minimizing the number of vias needed to route n two-terminal nets in a bounded routing region is shown to be NP-hard. However, in the case of a two-shore routing region, the topological via minimization problem can be solved in O(n/sup 2/ log n) time. As a basis for the algorithm, a two-chain maximum dominance problem, which is of interest in its own right, is considered, and its applications to other very large-scale integration layout problems are shown. >

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Citations
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Book

Algorithms for VLSI Physical Design Automation

TL;DR: This book is a core reference for graduate students and CAD professionals and presents a balance of theory and practice in a intuitive manner.
Journal ArticleDOI

Planarizing Graphs | A Survey and Annotated Bibliography

TL;DR: Given a nite, undirected, simple graph G, this work is concerned with operations on G that transform it into a planar graph and gives a survey of results about such operations and related graph parameters.
Proceedings ArticleDOI

A cell-replicating approach to minicut-based circuit partitioning

TL;DR: An extension to the Fiduccia and Mattheyses minicut algorithm (1982) allows cells to be replicated in both sides of the partition and can substantially reduce the number of cut nets in a partitioned network below what can be obtained without replication.
Journal ArticleDOI

Wirability of knock-knee layouts with 45 degrees wires

TL;DR: In this paper, the problem of wiring an arbitrary knock-knee layout (in a square grid with an arbitrary number of modules) in three and two layers using a small number of vias is investigated.
Journal ArticleDOI

An efficient algorithm for finding a maximum weight 2-independent set on interval graphs

TL;DR: With a slight extension and modification of the algorithm, the maximum weight k -independent set problem on an interval graph with n vertices can be solved in O ( n k ) time using O (n k ) space.
References
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Journal ArticleDOI

Planar Formulae and Their Uses

TL;DR: Using these results, it is able to provide simple and nearly uniform proofs of NP-completeness for planar node cover, planar Hamiltonian circuit and line, geometric connected dominating set, and of polynomial space completeness forPlanar generalized geography.
Proceedings ArticleDOI

Wire routing by optimizing channel assignment within large apertures

TL;DR: The purpose of this paper is to introduce a new wire routing method for two layer printed circuit boards based on the newly developed channel assignment algorithm and requires many via holes.
Journal ArticleDOI

New lower bound techniques for VLSI

TL;DR: This paper uses crossing number and wire area arguments to find lower bounds on the layout area and maximum edge length of a variety of new and computationally useful networks.
Journal ArticleDOI

Efficient Algorithms for Layer Assignment Problem

TL;DR: The layer assignment problem for interconnect is the problem of determining which layers should be used for wiring the signal nets and an efficient algorithm for identifying essential vias is presented and discussed in this paper.

Optimal layer assignment for interconnect

TL;DR: In this paper, le caractere NP-completite is shown to be in contradiction avec the conjecture du caractère NPcompletity, and the conjecture is disproved.