Journal ArticleDOI
A New PLA Design for Universal Testability
Reads0
Chats0
TLDR
A new design of universally testable PLA's is presented in which all multiple faults can be detected by a universal test set which is independent of the function being realized by the PLA.Abstract:
A new design of universally testable PLA's is presented in which all multiple faults can be detected by a universal test set which is independent of the function being realized by the PLA. The proposed design has the following properties. 1) It can be tested with function-independent test patterns; hence, no test pattern generation is required. 2) The amount of extra hardware is significantly decreased compared to the previous designs of universally testable PLA's. 3) Very high fault coverage is achieved, i. e., all single and multiple stuck faults, crosspoint faults, and adjacent line bridging faults are detected. 4) It is appropriate for built-in testing approaches. 5) It can be applied to the high-density PLA's using array folding techniques.read more
Citations
More filters
Book
Switching Theory for Logic Synthesis
TL;DR: Switching Theory for Logic Synthesis introduces and explains various topics that make up the subject of logic synthesis: multi-valued input two-valued output function, logic design for PLDs/FPGAs, EXOR-based design, and complexity theories of logic networks.
Journal ArticleDOI
Built-In Self-Test Structures
TL;DR: The various linear-feedback shift register designs for pseudorandom or pseudoexhaustive input test pattern generation and for output response signature analysis are presented.
Journal ArticleDOI
Implementing a Built-In Self-Test PLA Design
TL;DR: An NMOS implementation of a new built-in self-test PLA design is presented, which results in significantly better overhead than that of any existing scheme.
Proceedings Article
Lower overhead design for testability of programmable logic arrays
TL;DR: In this article, a technique for designing easily testable PLAs is presented, which consists of the addition of a small number of bit lines in such a way that, in test mode, any single product line can be activated and its associated circuitry and devices tested.
Journal ArticleDOI
Lower Overhead Design for Testability of Programmable Logic Arrays
Bozorgui-Nesbat,McCluskey +1 more
TL;DR: A new technique for designing easily testable PLA's is presented that consists of the addition of input lines in such a way that, in test mode, any single product line can be activated and its associated circuitry and device can be tested.
References
More filters
Journal ArticleDOI
Design for Testability—A Survey
TL;DR: The different techniques of design for testability are discussed in detail, including techniques which can be applied to today's technologies and techniques which have been recently introduced and will soon appear in new designs.
Journal ArticleDOI
Easily Testable Realizations ror Logic Functions
TL;DR: A realization for arbitrary logic function, using AND and EXCLUSIVE-OR gates, based on Reed-Muller canonic expansion is given that has many of these desirable properties of "easily testable networks".
Journal ArticleDOI
An introduction to array logic
Harold Fleisher,Leon I Maissel +1 more
TL;DR: In this paper, a detailed description of the nature of array logic is given, including general array structures and implementation, influence of decoder partitioning, design of logic arrays, output phase, "split" variables, feedback in logic arrays and reconfiguration.