Journal ArticleDOI
Implementing a Built-In Self-Test PLA Design
TLDR
An NMOS implementation of a new built-in self-test PLA design is presented, which results in significantly better overhead than that of any existing scheme.Abstract:
An NMOS implementation of a new built-in self-test PLA design is presented. The layouts for its additional test circuitry result in appoximately 15-percent overhead for most large PlAS, a significantly better overhead than that of any existing scheme. Both the input test patterns and the output responses, which are compressed intoastring of parity bits, are independent of the functions that the PLA realizes, and the 15-percent overhead includes the storage needed for the fault-free compressed output data. The fault coverage of this approach consists of all single and (1-2 -( 2n + m)) of all multiple stuck, crosspoint, and bridging faults in the original PLA and the additional test circuitry (n and m are the number of input variables and product terms, respectively). The article begins with a short review of existing design schemes.read more
Citations
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Patent
Programmable logic device
TL;DR: A programmable logic device architecture has a matrix of smaller functional units and a set of fixed conductive lines connected to the functional unit inputs and outputs forming programmable interconnection matrices.
Journal ArticleDOI
Test scheduling and control for VLSI built-in self-test
TL;DR: A hierarchical model for VLSI circuit testing is introduced and very efficient suboptimum algorithms are proposed for defining test schedules for both the equal length test and unequal length test cases.
Journal ArticleDOI
The Comparison Approach to Multiprocessor Fault Diagnosis
TL;DR: A system-level, comparison-based strategy for identifying faulty processors in a multiprocessor system is described and shown to correctly identify the set of faulty processors with a remarkably high probability, making it an attractive and viable addition or alternative to present fault diagnosis techniques.
Patent
Programmable logic array
TL;DR: In this article, a deterministic test pattern generator is used to generate test patterns such that each cross point in an AND-plane can be evaluated sequentially, where the final signature can be further compressed into only one bit.
Journal ArticleDOI
An effective BIST scheme for ROM's
Yervant Zorian,André Ivanov +1 more
TL;DR: A built-in self-test (BIST) scheme for ROMs that has very high fault coverage and very small likelihood of error escape (aliasing) is described.
References
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Journal ArticleDOI
An introduction to array logic
Harold Fleisher,Leon I Maissel +1 more
TL;DR: In this paper, a detailed description of the nature of array logic is given, including general array structures and implementation, influence of decoder partitioning, design of logic arrays, output phase, "split" variables, feedback in logic arrays and reconfiguration.
Journal ArticleDOI
Detection of Faults in Programmable Logic Arrays
TL;DR: A new fault model is proposed for the purpose of testing programmable logic arrays and it is shown that a test set for all detectable modeled faults detects a wide variety of other faults.
Journal ArticleDOI
Fault Analysis and Test Generation for Programmable Logic Arrays (PLA's)
Ostapko,Se June Hong +1 more
TL;DR: This work investigates shorts between the lines and crosspoint defects (spurious absence or presence), as well as stuck faults in a PLA, and shows that a complete crosspoint test set also detects most of all faults analyzed.
Journal ArticleDOI
A Design of Programmable Logic Arrays with Universal Tests
TL;DR: In this paper the problem of fault detection in easily testable programmable logic arrays (PLA's) is discussed and universal test sets to detect faults in PLA's are presented.
Journal ArticleDOI
A New PLA Design for Universal Testability
TL;DR: A new design of universally testable PLA's is presented in which all multiple faults can be detected by a universal test set which is independent of the function being realized by the PLA.