Journal ArticleDOI
A Parallel Adaptable Routing Algorithm and its Implementation on a Two-Dimensional Array Processor
TLDR
It is shown experimentally that routing by the proposed algorithm implemented on the AAP-1 is 230 times faster than a software maze router run on a 1-MIPS computer for a three-pin/net circuit on a 256 X 256 grid.Abstract:
A new parallel-processing wire-routing algorithm is presented and implemented on a parallel processor. The two main features of the parallel algorithm are the control of the path quality and the finding of a quasi-minimum Steiner tree. Both Lee's maze algorithm and the proposed algorithm are implemented on an AAP-1 two-dimensional array processor, and the performance is compared to that of software programming on a general-purpose computer. It is shown experimentally that routing by the proposed algorithm implemented on the AAP-1 is 230 times faster than a software maze router run on a 1-MIPS computer for a three-pin/net circuit on a 256 X 256 grid.read more
Citations
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Journal ArticleDOI
Recent advances in VLSI layout
Ernest S. Kuh,T. Ohtsuki +1 more
TL;DR: The current status of VLSI layout and directions for future research are addressed, and the field of computational geometry and its application to layout-in particular, to gridless routing and compaction-are reviewed, and layout engines are considered.
Proceedings ArticleDOI
A new look at hardware maze routing
TL;DR: This work refines the design of a hardware accelerator to support grid-based Maze Routing to substantially reduce the hardware requirements of each processing element while at the same time adding support for mulitilayer routing and fast iterative routing.
Proceedings ArticleDOI
PHIGURE: a parallel hierarchical global router
TL;DR: A new Parallel HIerarchical algorithm for Global Routing (PHIGURE) is presented, which includes structured hierarchical decomposition into separate independent tasks which are suitable for parallel execution and adaptive simplex solution for adding feedthroughs and adjusting channel heights for row-based layout.
Proceedings ArticleDOI
Acceleration of an FPGA router
P.K. Chan,Martine D. F. Schlag +1 more
TL;DR: A hardware accelerator is presented which exploits the fine-grain parallelism in routing individual nets and accelerates routing of FPGAs by 10 fold with a combination of processor clusters and hardware acceleration.
Proceedings ArticleDOI
Stochastic, spatial routing for hypergraphs, trees, and meshes
TL;DR: This paper shows how to accommodate fanout and how to achieve comparable route quality to software-based methods and how an FPGA implementation of the routing logic could route the Toronto Place and Route Benchmarks at least two orders of magnitude faster than a software Pathfinder while achieving within 3% of the aggregate quality.
References
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An Algorithm for Path Connections and Its Applications
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Proceedings ArticleDOI
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Proceedings ArticleDOI
A Parallel Bit Map Processor Architecture for DA Algorithms
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Proceedings ArticleDOI
Global Wiring on a Wire Routing Machine
TL;DR: A new global wiring algorithm designed for implementation on special purpose physical design machines that computes more accurate estimates of wiring channel demand and supply than other known algorithms.