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Proceedings ArticleDOI

A Simulator of Small-Delay Faults Caused by Resistive-Open Defects

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TLDR
This work couple the calculation of the critical size of a small-delay fault with the computation of the resistance range of the corresponding resistive-open defect for which this size is exceeded, and is able to extend probabilistic fault coverage metrics initially developed for static resistive bridging faults to small- delay defects.
Abstract
We present a simulator which determines the coverage of small-delay faults, i.e., delay faults with a size below one clock cycle, caused by resistive-open defects. These defects are likely to escape detection by stuck-at or transition fault patterns. For the first time, we couple the calculation of the critical size of a small-delay fault with the computation of the resistance range of the corresponding resistive-open defect for which this size is exceeded. By doing so, we are able to extend probabilistic fault coverage metrics initially developed for static resistive bridging faults to small-delay defects.

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Citations
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Proceedings ArticleDOI

Small-delay-fault ATPG with waveform accuracy

TL;DR: An automatic test pattern generation algorithm which considers waveforms and their propagation on each relevant line of the circuit and is capable of automatically generating a formal redundancy proof for undetectable small-delay faults; to the best of the knowledge this is the first such algorithm that is both scalable and complete.
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High-Throughput Logic Timing Simulation on GPGPUs

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Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model

TL;DR: A flow to extract, simulate and generate test patterns for interconnect open defects by employing an aggressive fault collapsing strategy and an optimized fault list ordering heuristic which allows to combine the advantages of event-driven simulation with bit parallelism is presented.
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GPU-Accelerated Simulation of Small Delay Faults

TL;DR: By exploiting multiple dimensions of parallelism from gates, faults, waveforms, and circuit instances, the proposed approach allows for timing-accurate and exhaustive small delay fault simulation under process variation for designs with millions of gates.
Proceedings ArticleDOI

GPU-accelerated small delay fault simulation

TL;DR: This work presents a waveform-accurate approach for fast high-throughput small delay fault simulation on Graphics Processing Units (GPUs) that enables accurate exhaustive small delay faults simulation even for multimillion gate designs without fault dropping for the first time.
References
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Proceedings ArticleDOI

High volume microprocessor test escapes, an analysis of defects our tests are missing

TL;DR: In this paper, defects found in a high volume microprocessor when shipping at a low defect level are explored to forecast the need for better tools and methods to earlier achieve high quality goals.
Journal ArticleDOI

Resistance characterization for weak open defects

TL;DR: Characterizing weak opens can help researchers assess the need for delay fault tests, and it is shown that strong open defects can cause a circuit to malfunction, but even weak open defects could cause it to function poorly.
Proceedings ArticleDOI

Testing for resistive opens and stuck opens

TL;DR: The effects on test results of three test conditions as well as test patterns applied are evaluated and five Murphy chips are diagnosed as having stuck open defects and one chip is diagnosed asHaving a resistive open defect.
Proceedings ArticleDOI

Defect-based delay testing of resistive vias-contacts a critical evaluation

TL;DR: In this paper, a defect-based study analyzes statistical signal delay properties and delay fault test pattern constraints in the CMOS deep submicron environment, where CMOS resistive vias and contacts were used as a delay defect target.
Proceedings ArticleDOI

A persistent diagnostic technique for unstable defects

TL;DR: A technique using the layout information for an open fault diagnosis, and a testing method for the delay fault are discussed, and some experimental results of actual chips are shown.