Journal ArticleDOI
Adiabatic dynamic logic
TLDR
In this article, the authors describe a new CMOS logic family-adiabatic dynamic logic (ADL)-that is the result of combining adiabatic theory with conventional CMOS dynamic logic.Abstract:
With adiabatic techniques for capacitor charging, theory suggests that it should be possible to build gates with arbitrarily small energy dissipation. In practice, the complexity of adiabatic approaches has made them impractical. We describe a new CMOS logic family-adiabatic dynamic logic (ADL)-that is the result of combining adiabatic theory with conventional CMOS dynamic logic. ADL gates are simple, general, readily cascadable, and may be fabricated in a standard CMOS process. A chain of 1000 ADL inverters has been constructed in 0.9 /spl mu/m CMOS and successfully tested at 250 MHz. This result, together with comprehensive circuit simulation, suggest that ADL offers an order of magnitude reduction in power consumption over conventional CMOS circuitry. >read more
Citations
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Journal ArticleDOI
An efficient charge recovery logic circuit
Yong Moon,Deog-Kyoon Jeong +1 more
TL;DR: Efficient charge recovery logic (ECRL) is proposed as a candidate for low-energy adiabatic logic circuit and shows four to six times power reduction with a practical loading and operation frequency range.
Journal ArticleDOI
Pass-transistor adiabatic logic using single power-clock supply
TL;DR: In this article, a pass-transistor adiabatic logic (PAL) was proposed to operate from a single power-clock supply and outperforms the previously reported adiabilistic logic techniques in terms of its energy use.
Proceedings ArticleDOI
2nd order adiabatic computation with 2N-2P and 2N-2N2P logic circuits
TL;DR: This paper introduces a new class of adiabatic computing circuits which have several advantages over existing approaches, the primary one being that, because no diodes are used, switching energy can be reduced to an energy of O(CV t) over conventional CMOS.
Proceedings ArticleDOI
Ultra-low power digital subthreshold logic circuits
Hendrawan Soeleman,Kaushik Roy +1 more
TL;DR: This paper analyzes both CMOS and Pseudo-NMOS logic families operating in the subthreshold region and compares the results with CMOS in the normal strong inversion region and with other known low-power logic, namely, energy recovery logic.
Journal ArticleDOI
Clocked CMOS adiabatic logic with integrated single-phase power-clock supply
TL;DR: CAL is a dual-rail logic that operates from a single-phase AC power-clock supply that makes it possible to integrate all power control circuitry on the chip, resulting in better system efficiency, lower cost, and simpler power distribution.
References
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Reversible electronic logic using switches
TL;DR: In this paper, two methods of using switches to implement reversible computations are discussed, one is basically an extension to "pass logic" which has been previously used with both nMOS and CMOS transmission gates to achieve low energy dissipation.
Proceedings ArticleDOI
Adiabatic Switching, Low Energy Computing, And The Physics Of Storing And Erasing Information
J.G. Koller,W.C. Athas +1 more
TL;DR: The principles of the new CMOS logic family are sketched, and some intuitive insights which might be useful in constructing a rigorous proof of a switching-theoretic analog of Landuaer's principle are discussed.
Practical implementation of charge recovering asymptotically zero power CMOS
Saed G. Younis,Thomas F. Knight +1 more
Hot Clock nMOS
Charles L. Seitz,Alexander H. Frey,Sven Mattisson,Steve D. Rabin,Don A. Speck,Jan L. A. van de Snepscheut +5 more
TL;DR: The Hot-Clock nMOS as discussed by the authors is a style of design that has advantages in circuit energetics and performance that has been used in numerous small projects and test structures, and in 3 substantial projects fabricated through MOSIS.
Proceedings ArticleDOI
An energy-efficient CMOS line driver using adiabatic switching
TL;DR: The authors describe the adiabatic charging principle used, which allows a digital circuit designer to directly trade off switching time for increased energy efficiency.