Proceedings ArticleDOI
An efficient implementation of floating point multiplier
Mohamed Al-Ashrafy,Ashraf Salem,Wagdy R. Anis +2 more
- pp 1-5
TLDR
An efficient implementation of an IEEE 754 single precision floating point multiplier targeted for Xilinx Virtex-5 FPGA using VHDL to implement a technology-independent pipelined design.Abstract:
In this paper we describe an efficient implementation of an IEEE 754 single precision floating point multiplier targeted for Xilinx Virtex-5 FPGA. VHDL is used to implement a technology-independent pipelined design. The multiplier implementation handles the overflow and underflow cases. Rounding is not implemented to give more precision when using the multiplier in a Multiply and Accumulate (MAC) unit. With latency of three clock cycles the design achieves 301 MFLOPs. The multiplier was verified against Xilinx floating point multiplier core.read more
Citations
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Journal ArticleDOI
Design of area and power efficient Radix-4 DIT FFT butterfly unit using floating point fused arithmetic
E Prabhu,H. Mangalam,S. Karthick +2 more
TL;DR: In this work, power efficient butterfly unit based FFT architecture is presented and it is observed that the Radix-4 DIT fused floating-point FFT butterfly requires 50.17% less space and 12.16% reduced power compared to the existing methods.
Proceedings ArticleDOI
Design and synthesis of goldschmidt algorithm based floating point divider on FPGA
TL;DR: The main objective is to synthesize the proposed floating point divider on FPGA using Verilog hardware description language (HDL), which can be used in the design of floating point divide - add fused (DAF) architecture.
Proceedings ArticleDOI
An Approximate and Iterative Posit Multiplier Architecture for FPGAs
TL;DR: This paper is the first work that proposes a hardware architecture of an approximate and iterative posit multiplier, and the appropriate balance between latency and accuracy can be finely determined at runtime.
Journal ArticleDOI
A novel power efficient 0.64-GFlops fused 32-bit reversible floating point arithmetic unit architecture for digital signal processing applications
TL;DR: Simulation results and comparative studies demonstrate that the proposed unit efficiently utilizes the number of gates, has reduced quantum cost and produced less garbage outputs with low latency, thereby making the design a computational and power efficient one.
Proceedings ArticleDOI
Design and verification of Dadda algorithm based Binary Floating Point Multiplier
TL;DR: A fast single precision floating point multiplier that achieves maximum frequency of 851 MHz with 433 slices area and 1230 LUT-flip flop pairs in Virtex6 family is presented.
References
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Book
Digital Signal Processing: Principles, Algorithms, and Applications
TL;DR: This paper presents a meta-analysis of the Z-Transform and its application to the Analysis of LTI Systems, and its properties and applications, as well as some of the algorithms used in this analysis.
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Computer Organization and Design: the Hardware/Software Interface
TL;DR: The third edition of the book as mentioned in this paper has been updated with new pedagogical features, such as new information and challenging exercises for the advanced student, as well as a complete index of the material in the book and on the CD appears in the printed index.
[서평]「Computer Organization and Design, The Hardware/Software Interface」
TL;DR: Recognizing the mannerism ways to get this books computer organization and design the hardware software interface 4th fourth edition by patterson hennessy is additionally useful.
Proceedings ArticleDOI
Quantitative analysis of floating point arithmetic on FPGA based custom computing machines
TL;DR: Using higher-level languages, like VHDL, facilitates the development of custom operators without significantly impacting operator performance or area, as well as properties, including area consumption and speed of working arithmetic operator units used in real-time applications.