Proceedings ArticleDOI
An efficient implementation of floating point multiplier
Mohamed Al-Ashrafy,Ashraf Salem,Wagdy R. Anis +2 more
- pp 1-5
TLDR
An efficient implementation of an IEEE 754 single precision floating point multiplier targeted for Xilinx Virtex-5 FPGA using VHDL to implement a technology-independent pipelined design.Abstract:
In this paper we describe an efficient implementation of an IEEE 754 single precision floating point multiplier targeted for Xilinx Virtex-5 FPGA. VHDL is used to implement a technology-independent pipelined design. The multiplier implementation handles the overflow and underflow cases. Rounding is not implemented to give more precision when using the multiplier in a Multiply and Accumulate (MAC) unit. With latency of three clock cycles the design achieves 301 MFLOPs. The multiplier was verified against Xilinx floating point multiplier core.read more
Citations
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Synthesis of double precision float- ing point multiplier using vhdl
TL;DR: In this paper, pipelining technique is used for Synthesis of double precision floating point multiplier using VHDL and the double precision FPM targeted on a Xilinx Virtex-6 xc6vlx75t-3ff484 device is presented.
Proceedings ArticleDOI
Porting A Convolutional Neural Network For Stereo Vision In Hardware
TL;DR: In this article, the authors analyze, reconstruct and reevaluate a pretrained CNN for stereo matching and develop a hardware architecture to be used in an FPGA so as to compute the stereo estimation of still images in real time in hardware.
Journal ArticleDOI
FPGA Implementation of Single Precision Floating Point Multiplier Using High Speed Compressors
Im. Lavanya,A. M. Guna Sekhar +1 more
TL;DR: The concepts of High speed compressors are used for the implementation of a High speed single precision binary Floating point multiplier by using IEEE 754 standard, which makes the multiplier faster as compared to the conventional multiplier.
Journal ArticleDOI
Performance Analysis of Floating Point MAC Unit
TL;DR: In this research work MAC unit is proposed, which consists of Multiplier, adder and an accumulator unit and various floating point multiplier architectures used in MAC unit are pipelined Floating point multiplier; carry save, carry look ahead and ripple carry multipliers.
Journal ArticleDOI
An Efficient Implementation of Double Precision Floating Point Multiplier Using Booth Algorithm
TL;DR: This paper presents the floating point multiplier that supports the IEEE 754 binary interchange format and is compared with Radix-4 Booth Multiplier, which also handles overflow and underflow cases.
References
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Digital Signal Processing: Principles, Algorithms, and Applications
TL;DR: This paper presents a meta-analysis of the Z-Transform and its application to the Analysis of LTI Systems, and its properties and applications, as well as some of the algorithms used in this analysis.
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Computer Organization and Design: the Hardware/Software Interface
TL;DR: The third edition of the book as mentioned in this paper has been updated with new pedagogical features, such as new information and challenging exercises for the advanced student, as well as a complete index of the material in the book and on the CD appears in the printed index.
[서평]「Computer Organization and Design, The Hardware/Software Interface」
TL;DR: Recognizing the mannerism ways to get this books computer organization and design the hardware software interface 4th fourth edition by patterson hennessy is additionally useful.
Proceedings ArticleDOI
Quantitative analysis of floating point arithmetic on FPGA based custom computing machines
TL;DR: Using higher-level languages, like VHDL, facilitates the development of custom operators without significantly impacting operator performance or area, as well as properties, including area consumption and speed of working arithmetic operator units used in real-time applications.