Proceedings ArticleDOI
An efficient implementation of floating point multiplier
Mohamed Al-Ashrafy,Ashraf Salem,Wagdy R. Anis +2 more
- pp 1-5
TLDR
An efficient implementation of an IEEE 754 single precision floating point multiplier targeted for Xilinx Virtex-5 FPGA using VHDL to implement a technology-independent pipelined design.Abstract:
In this paper we describe an efficient implementation of an IEEE 754 single precision floating point multiplier targeted for Xilinx Virtex-5 FPGA. VHDL is used to implement a technology-independent pipelined design. The multiplier implementation handles the overflow and underflow cases. Rounding is not implemented to give more precision when using the multiplier in a Multiply and Accumulate (MAC) unit. With latency of three clock cycles the design achieves 301 MFLOPs. The multiplier was verified against Xilinx floating point multiplier core.read more
Citations
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Proceedings ArticleDOI
Area and time optimized realization of 16 point FFT and IFFT blocks by using IEEE 754 single precision complex floating point adder and multiplier
TL;DR: Analysis of the obtained results show that the proposed design of the complex floating point multiplier as compared to the existing design, is optimal in terms of number of cells, number of gates, path delay, cell area and produces highly precise results.
Proceedings ArticleDOI
A high speed area efficient FIR filter using floating point dadda algorithm
V.M. Dhivya,A. Sridevi,A. Ahilan +2 more
TL;DR: This work deals with Dadda multiplier based FIR filter which consumes low power with high performance and Transposed form of FIR filter is taken to evaluate the efficiency of floating point multiplier using DaddA algorithm.
Journal ArticleDOI
Novel chaotic random memory indexing steganography on FPGA
TL;DR: Two novel image steganography algorithms are proposed based on generalized chaotic maps based on the generalization technique of logistic maps adding extra degrees of freedom for the design of different chaotic behaviors, thus enhancing the security levels of the proposed algorithms.
Proceedings ArticleDOI
A Hardware Generator for Posit Arithmetic and its FPGA Prototyping
TL;DR: In this article, a 16 and 32-bit posit adder/subtractor and multiplier with different exponent size (ES) have been designed for the Xilinx Virtex-7 xc7vx330t-3ffg1157 device.
Journal ArticleDOI
Design and Synthesis of Single Precision Floating Point Division based on Newton-Raphson Algorithm on FPGA
TL;DR: This paper describes a single precision floating point division based on Newton-Raphson computational division algorithm, designed using a 24-bit Vedic multiplication (Urdhva-triyakbhyam-sutra) technique and verified on Xilinx Spartan 6 SP605 Evaluation Platform FPGA.
References
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Book
Digital Signal Processing: Principles, Algorithms, and Applications
TL;DR: This paper presents a meta-analysis of the Z-Transform and its application to the Analysis of LTI Systems, and its properties and applications, as well as some of the algorithms used in this analysis.
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Computer Organization and Design: the Hardware/Software Interface
TL;DR: The third edition of the book as mentioned in this paper has been updated with new pedagogical features, such as new information and challenging exercises for the advanced student, as well as a complete index of the material in the book and on the CD appears in the printed index.
[서평]「Computer Organization and Design, The Hardware/Software Interface」
TL;DR: Recognizing the mannerism ways to get this books computer organization and design the hardware software interface 4th fourth edition by patterson hennessy is additionally useful.
Proceedings ArticleDOI
Quantitative analysis of floating point arithmetic on FPGA based custom computing machines
TL;DR: Using higher-level languages, like VHDL, facilitates the development of custom operators without significantly impacting operator performance or area, as well as properties, including area consumption and speed of working arithmetic operator units used in real-time applications.