Proceedings ArticleDOI
An efficient implementation of floating point multiplier
Mohamed Al-Ashrafy,Ashraf Salem,Wagdy R. Anis +2 more
- pp 1-5
TLDR
An efficient implementation of an IEEE 754 single precision floating point multiplier targeted for Xilinx Virtex-5 FPGA using VHDL to implement a technology-independent pipelined design.Abstract:
In this paper we describe an efficient implementation of an IEEE 754 single precision floating point multiplier targeted for Xilinx Virtex-5 FPGA. VHDL is used to implement a technology-independent pipelined design. The multiplier implementation handles the overflow and underflow cases. Rounding is not implemented to give more precision when using the multiplier in a Multiply and Accumulate (MAC) unit. With latency of three clock cycles the design achieves 301 MFLOPs. The multiplier was verified against Xilinx floating point multiplier core.read more
Citations
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Speed optimization of 32 bit single precision floating point multiplier through pipelining in VHDL
TL;DR: The architectural method for speed optimization of floating point multiplier involves increasing the frequency by implementing pipelines in the design using VHDL language and handles the overflow/ underflow cases with normalization for the better accuracy of the result.
Journal ArticleDOI
Ultrafast dynamic machine vision with spatiotemporal photonic computing
TL;DR: In this article , a spatiotemporal photonic computing architecture is proposed to match the highly parallel spatial computing with high-speed temporal computing and achieve a threedimensional spatio-temporal plane.
Empirical Review of Low Power Column by Pass Multiplier
B. K Sharma,M. Tech +1 more
TL;DR: A modified structure with reduced switching activity is presented through optimization of design to scale back the facility consumption of multiplier factor booth coding methodology.
Book ChapterDOI
Low-Power and Area-Efficient Design of Higher-Order Floating-Point Multipliers Using Vedic Mathematics
TL;DR: A IEEE 754 single precision floating-point multiplier with the integer multiplication being carried out in a vedic mathematics style using different sutras is designed and compared with conventional implementations using Booth and array multipliers.
References
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Digital Signal Processing: Principles, Algorithms, and Applications
TL;DR: This paper presents a meta-analysis of the Z-Transform and its application to the Analysis of LTI Systems, and its properties and applications, as well as some of the algorithms used in this analysis.
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Computer Organization and Design: the Hardware/Software Interface
TL;DR: The third edition of the book as mentioned in this paper has been updated with new pedagogical features, such as new information and challenging exercises for the advanced student, as well as a complete index of the material in the book and on the CD appears in the printed index.
[서평]「Computer Organization and Design, The Hardware/Software Interface」
TL;DR: Recognizing the mannerism ways to get this books computer organization and design the hardware software interface 4th fourth edition by patterson hennessy is additionally useful.
Proceedings ArticleDOI
Quantitative analysis of floating point arithmetic on FPGA based custom computing machines
TL;DR: Using higher-level languages, like VHDL, facilitates the development of custom operators without significantly impacting operator performance or area, as well as properties, including area consumption and speed of working arithmetic operator units used in real-time applications.