An Introduction to Reversible Latches
J. E. RICE
*
Department of Mathematics & Computer Science, University of Lethbridge, Lethbridge, AB, Canada
*Corresponding author: j.rice@uleth.ca
Reversible logic has been suggested as one solution to the problem of power consumption in today’s
electronic devices. This paper addresses the issue of designing reversible latches and provides an
overview and analysis of some proposed designs.
Keywords: Boolean logic circuits; reversible logic; sequential circuits
Received 11 April 2007; revised 1 October 2007
1. INTRODUCTION
Many of us have likely experienced the frustration of one’s
cell phone battery dying, or running low on battery power
for your laptop when there is no plug-in available. Electronic
devices have become portable, and are intended to be
taken everywhere. The problem is that there is not always a
source of electricity available, and so the demand for
devices that use less power, so that batteries last longer, is
quickly growing. Some researchers believe that the well-
known Moore’s law is at an end due to the inability for us
to deal with the power-requirements of future chips [1]. For
decades now the electronics industry has been able to
produce devices that are smaller, faster and use less power
year after year. Now, however, we may have hit a brick
wall, and incremental improvements will bring only small
advances.
An entirely new paradigm may provide the solution. The
use of reversible logic in building chips may provide a
solution. As stated by Frank [2],
... computers based mainly on reversible logic
operations can reuse a fraction of the signal energy that
theoretically can approach arbitrarily near to 100% as
the quality of the hardware is improved...
He and many other researchers believe that we are coming
close to having technologies that will support reversible
computing, and that reversible devices will have far lower
power requirements than do traditional devices. Additionally,
a most prominent application of reversible logic lies in
quantum computers, and in fact reversible logic has been
called “quantum computing’s practical cousin” [3]. As
Thapliyal et al. describe, a quantum computer will be
viewed as a quantum network composed of quantum logic
gates [4]. Each gate will be designed to perform some elemen-
tary operation on quantum systems called qubits. Each qubit
represents an elementary unit of information that can be
thought of as corresponding to the traditional bit values of 0
and 1. These operations must be unitary, and any unitary oper-
ation is reversible. However, traditional designs for arithmetic
operations such as addition and multiplication make heavy use
of irreversible logic gates such as AND and OR. Thus,
quantum arithmetic must be built from reversible logical
components.
The idea of reversible computing was discussed many
years ago by Landauer [5] and Bennett [6], and further
refined by Toffoli [7]. Recent work has focused heavily on
synthesis techniques for reversible logic. Partly because
fan-outs are not permitted in reversible logic circuits, the
synthesis process for reversible logic differs significantly
from that of traditional irreversible logic. Research in this
area is following many directions, some of which are detailed
in [8 –15], and implementations have been suggested by
[16–19], to name a few. There is, however, little mention of
sequential logic in a reversible context, and it is this area
that this work addresses.
We first address the issues that some researchers raise
regarding the notion of sequential logic in a reversible
context. For instance, it can be argued that the very model
of quantum computing is so different from that of traditional
computing that the state machine model upon which sequen-
tial circuits have been based will be made obsolete. Another
problem that has been raised is that in quantum computation
models data are stored in qubits, for which there is no
known method of implementing feedback. There are,
however, other possible models that reversible logic can be
based upon, although we leave that particular investigation
for other work. To further refute the claim that sequential
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reversible networks are not possible, we refer to Frank’s
2005 paper entitled ‘Approaching the Physical Limits of
Computing’. In this work Frank states that
The true requirement that must be imposed on the logical
functionality of a reversible logic gate is simply this:
that for each distinct operation that the gate can be
directed to perform, no two initial logical states ...that
can possibly arise in the normal course of the machine’s
operation ...can be transformed to the same final
state [1].
Given this, Frank goes on to describe a number of possible gate
behaviours, including reversible SET and conditional rever-
sible SET gates. The latter of these requires knowledge of the
initial condition of the state, much like a traditional latch.
Thus we argue that it is not the concept of a reversible sequen-
tial network that is in question, but simply the implementation;
that is, the target technology. At this juncture implementing
technologies for reversible logic are still in the realm of the
unknown, and so we choose not to limit ourselves to those
few suggestions that have been proposed in this area.
It may indeed be the case that the future models of comput-
ing evolve to be very different from the traditional state
machine-based models that we rely upon today; however,
we believe that even if this is the case then during an industry
switch from traditional computing models to new models a
transition period will be necessary. Work such as this may
fill in the gaps in our knowledge and provide a smoother
transition during such a period.
The small amount of previous work in the area of synthesis
for sequential reversible logic includes [4, 20 –24]. Many of
these papers suggest designs for reversible memory elements,
and in some cases the design investigated is that of a basic
latch, as in this paper. In this work, we review and analyse
the simplest of the proposed designs, the SR latch.
2. BACKGROUND
2.1. Reversible logic
We first present some basic concepts underlying the idea of
reversible logic. According to Shende et al. , the following
definition holds.
D
EFINITION 2.1. A gate is reversible if the (Boolean)
function it computes is bijective [13].
In other words, a function is reversible if there is a
one-to-one and on-to mapping from the inputs to the outputs
(and vice versa) of the function. At the very least, a reversible
function must have the same number of inputs as it does
outputs. For instance, the traditional NOT gate is reversible,
but the traditional AND gate is not, as shown in Table 1.
We can see how the NOT gate is bijective; for each value
of x there is a unique value for x
¯
and every value of x
¯
results from applying the function to x. However, the AND
gate is not bijective as there are two values for yz that result
in the same output, and so it is not injective and cannot be
bijective.
There are, however, a variety of possibilities for Boolean
reversible functions, even limiting ourselves to a few inputs
(e.g. three). Table 2 lists the behaviour of each of the most
commonly used reversible gates. The behaviour describes
how each input becomes transformed to produce the outputs
when the gate is applied. The swap and Not gates are the
very simplest, with the Feynman, Toffoli and Fredkin in
essence extending these basic gates to incorporate additional
inputs. This work concentrates primarily on latches designed
from Fredkin and Toffoli gates, and the symbols used for
these gates are shown in Fig. 1. The inputs and outputs in
Fig. 1 are labelled in such a way to provide a reminder of
the behaviour of the gates. Thus in Fig. 1(A), we see that
the topmost signal passes through the gate unchanged, as indi-
cated by the fact that it is labelled as x on both sides of the gate.
The same holds true for the next signal, y, while the third
signal is affected by the gate as described by the equation
given on the right side of the gate. For instance, if the input
values for x, y and z are 110 then the output values will be
x, y, xy z or 111 after the Toffoli gate is applied.
TABLE 1. The truth tables for the
traditional NOT and AND gates.
xx
¯
yzy
.
z
01 000
10 010
100
111
TABLE 2. The behaviour of a selection of
more commonly used reversible logic gates.
Gate Behaviour
Not (x) ! (x 1)
Feynman (x, y) ! (x, x y)
Toffoli (x, y, z) ! (x, y, xy z)
swap (x, y) ! (y, x)
Fredkin (x, y, z) ! (x, z, y) iff x ¼ 1
FIGURE 1. (A) The symbol for the Toffoli gate. (B) The symbol for
the Fredkin gate.
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THE COMPUTER JOURNAL, Vol. 51 No. 6, 2008
2.2. Latches
The current model of computing is based on the concept of a
state machine. Such a machine exhibits different behaviours
depending on the value of its current state. Thus, some struc-
ture is required to keep track of this state. The basic building
block used in today’s computer is the flip-flop, which them-
selves are built out of latches. There are a variety of types of
latches, but the basic type upon which other designs are
generally modified is the Set-Reset, or SR latch. A SR latch
allows the outputs, labelled Q
þ
and Q
þ
, to either be ‘set’, in
which case the next state values are Q
þ
¼ 1 and Q
þ
¼ 0or
‘reset’, in which case Q
þ
¼ 0 and Q
þ
¼ 1. The primary
inputs of such a structure are S (set) and R (reset). A
diagram illustrating a NOR-gate implementation of a SR
latch is given in Fig. 2(A).
A variety of reversible latches have been introduced in pre-
vious work. This paper examines the behaviour of the latches
presented in [22]. These reversible latches have been designed
to emulate a traditional SR latch. The behaviour of the SR
latch is characterized by the truth table given in Table 3.
2.3. Previous work
A number of researchers including Toffoli [7] and Frank [1]
discuss the potential for sequential reversible logic, but do
not present any structures for its realization. Fredkin and
Toffoli [25] appear to be the first to suggest a conservative
logic sequential element in the form of a JK
¯
flip-flop,
and Picton [23] suggests a reversible SR latch. He uses the
basic Fredkin gate to build this latch, as shown in Fig. 2(B).
This work also concentrates on the use of a basic memory
element such as the SR latch, as it is the traditional
building block for the clocked flip-flop structures that are
our eventual goal.
3. REVERSIBLE LATCHES
In this work we will introduce, characterize and analyse the
behaviour of two reversible latch designs: the Toffoli-based
latch shown in Fig. 3(A) and the Fredkin-based latch shown
in Fig. 3(B). As noted in the section above, Picton was the
first to introduce a reversible latch based on Fredkin gates.
However, if we examine the illustration of his latch in Fig. 2
we see that, like the traditional latch, the design requires
fan-out from the signals for Q
þ
and Q
þ
. The problem with
Picton’s model is that the concept of reversible logic is predi-
cated on the fact that not only can one not allow the destruc-
tion of data (e.g. a signal value), as in the situation with the
traditional AND gate, but one can not allow the arbitrary
creation of data. This means that fan-out is not permitted.
However, the problem can be corrected by making use of
one of the garbage outputs, and in fact the design in Fig. 3
(B) does exactly this.
Thapliyal, Srinivas and Zwolinski [4] have also published
work in the area of sequential reversible logic, and have intro-
duced their own constructions of basic memory elements such
as flip-flops. However, their designs are ultimately different
from those presented in this work, although possibly useful
for comparison purposes.
3.1. The Fredkin-based SR latch
The Fredkin-based SR latch was developed by using Picton’s
original latch as a reference, and addressing the problem
of fan-out in his design. As indicated above, the solution
suggested here is to make use of one of the unused outputs
of the Fredkin gate for one of these purposes. The modified
design is as shown in Fig. 3(A). Table 4 shows that this
design does, in fact, satisfy the requirements for the behaviour
of a SR latch. There are 16 possible starting values of the
FIGURE 2. The SR latch (A) built from traditional logic gates and
(B) built from two Fredkin gates as designed by Picton [23].
TABLE 3. The next state
values for the SR latch.
Inputs
SR
Next state
Q
þ
Q
þ
00 QQ
¯
01 01
10 10
1 1 not permitted
FIGURE 3. (A) SR latch based on Toffoli gates. (B) SR latach based
on Fredkin gates.
702 J. E. RICE
THE COMPUTER JOURNAL, Vol. 51 No. 6, 2008
inputs to the Fredkin latch, as shown in Table 4. For some
input combinations there may be a delay while the gates
process the initial values, then the new values are propagated
back to the inputs and another processing step must take place.
Additionally, some input combinations will cause the latch to
oscillate between two non-meaningful states. We are most
interested in ascertaining that the latch carries out the beha-
viour detailed in the characteristic table of the SR latch
(Table 3).
Let us first examine what occurs when S and R are both set
to 0. What should happen is that the current state of the latch
(that is, the current values for Q and Q
¯
) is reflected in the next
state (that is, the values for Q
þ
and Q
þ
). It appears that this
does occur for all possible initial values of Q and Q
¯
if we
simply look at the values after gate processing for Q
þ
and
Q
þ
. Actually, due to the nature of the Fredkin gate, Q
þ
will
always reflect the unchanged value of Q, and similarly for Q
¯
and
Q
þ
. It is more important to look at the new input
values, as this tells us whether the latch will be stable at its
current values, or if the values will change after the next
gate processing step. We see in lines 1 and 2 of Table 4 that
the new input values for Q and Q
¯
are the same as the original
values, and this tells us two things: that the latch will be stable,
or remain unchanged after the next processing step, and that
the behaviour is correct in that the current values of Q and
Q
¯
are stored unchanged in the latch. However, in lines 0 and
3 we see that the new input values for Q and Q
¯
are not the
same as the original values. In fact, if the latch somehow
gets into a non-meaningful state where Q ¼ Q
¯
and we set
S ¼ R ¼ 0 the latch will oscillate between QQ
¯
¼ 00 and
QQ
¯
¼ 11. This does not strictly match the description in the
characteristic table, but we assume that this will not matter
since the latch should never be in this type of non-meaningful
state.
Lines 4– 7 of the table allow us to verify the correct ‘reset’
behaviour for the latch; that is, when SR ¼ 01 the latch should
have values of Q
þ
Q
þ
¼ 01, and Table 4 shows that this does
happen, eventually, for all possible initial values of Q and Q
¯
.
Similarly lines 8 –11 verify the ‘set’ behaviour of the latch.
Lines 12 –15 are not particularly useful in that they show
what will occur when S and R are both set to 1, which is in
fact, a combination that should not be permitted.
In general, however, Table 4 shows that for all ‘permitted’
combinations for S and R and all meaningful initial values of
Q and Q
¯
the latch will eventually reach the desired stable state.
3.2. The Toffoli-based SR latch
One approach to determining reversible memory elements is
to take existing memory elements, built from traditional
logic, and replace the traditional components with reversible
components. For instance, the NOR gate may be used in the
design of the SR latch, as is shown in Fig. 2(A). The NOR
gate is clearly not reversible; one problem is that there is
only one output and two inputs. Table 5(A) shows one possible
way to create a reversible equivalent of the NOR gate’s beha-
viour. Note that for our use of this gate we will always set the z
input to 0, and so we have shown the four inputs with z ¼ 0at
the top of the truth table. Since we now have a reversible NOR
gate we can create a reversible latch out of it, as shown in
Fig. 4(A). However we have, again run into the problem of
fan-out, and so Fig. 4(B) shows a reversible latch based on
the reversible NOR gate without fan-out. The reversible
latch shown in Fig. 4 is perfectly acceptable, however, it
turns out that a small modification to the reversible NOR
gate—inverting the x and y inputs—will turn it into a
Toffoli gate, and so the Toffoli-based latch shown in
Fig. 3(A) is, in fact, the equivalent of this ‘revnor’-based latch.
Having thus shown the development of the Toffoli-based
SR latch we will now turn to verifying its behaviour. As for
TABLE 4. Behaviour of the Toffoli-based SR latch.
Initial
values
After gate
processing
New input
values
SR11QQS
þ
R
þ
g
1
g
2
Q
þ
Q
þ
SR11QQ
0 001100 001100 001111
1 001101 000101 001101
2 001110 011010 001110
3 001111 110011 001100
4 011100 011100 011111
5 011101 110101 011101
6 011110 011110 011111
7 011111 110111 011101
8 101100 101100 101111
9 101101 101101 101111
10 10 11 10 11 10 10 10 11 10
11 10 11 11 11 10 11 10 11 10
12 11 11 00 11 11 00 11 11 11
13 11 11 01 11 11 01 11 11 11
14 11 11 10 11 11 10 11 11 11
15 11 11 11 11 11 11 11 11 11
TABLE 5. Truth tables for (A) the traditional,
irreversible NOR gate, and (B) a reversible equivalent.
xy
x þ y xyz xy (x þ y) z
00 1 000 00 1
01 0 010 01 0
10 0 100 10 0
11 0 110 11 0
001 00 0
011 01 1
101 10 1
111 11 1
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THE COMPUTER JOURNAL, Vol. 51 No. 6, 2008
the Fredkin-based latch, there are 16 possible combinations.
These are shown in Table 6. The reader will note that the
ordering in which the inputs are given does not match that
of Table 4, and that is because negated input values for S
and R are required. The ordering shown for each of Tables 4
and 6 gives results for keeping the latch unchanged in lines
0–3, the reset operation in lines 4 –7, and the reset operation
in lines 8–11. We can see that the behaviour for the Toffoli
latch does match that of the Fredkin latch as well as meeting
the requirements for a SR latch. As we saw for the Fredkin
latch, some input combinations result in the desired behaviour
immediately after the gates process the inputs, while others
require an additional gate-processing step before the desired
behaviour is seen. Again, some input combinations cause the
latch to oscillate between two non-meaningful states as we
see in lines 0 and 3.
3.3. A short comparison of the Fredkin and
Toffoli designs
Given that we have three possible reversible designs for a SR
latch, how might one choose between them? Two criteria
come to mind in making a selection: (1) behaviour and (2)
speed.
3.3.1. Behaviour compari son
All three of the suggested latches behave in similar ways:
† the latches store values of QQ
¯
¼ 01 and QQ
¯
¼ 10, but
become unstable if required to store non-meaningful
values such as QQ
¯
¼ 00 or QQ
¯
¼ 11,
† the latches will all reset or set the latch appropriately
for any given starting values for Q and Q
¯
, and
† the latches will all result in some stable but non-
meaningful state when S ¼ R ¼ 1.
The only difference is that when S ¼ R ¼ 1 the resulting
values for Q
þ
and Q
þ
are 11 for the Toffoli latch and 00 for
both the revnor-based latch and the Fredkin latch.
3.3.2. Timing comparison
As indicated above, there is in some cases a delay before the
desired results become evident. For instance, for the input
combination SRQQ
¯
¼ 0100, the immediate result for the
Fredkin latch is that Q
þ
Q
þ
is set to 00. However, after the
new output values are propagated back to the inputs and an
additional gate processing step takes place, then the desired
values of Q
þ
Q
þ
¼ 01 are seen.
Interestingly enough, it turns out that both the Toffoli and
the Fredkin-based latches behave in very similar ways; that
is, an extra step of processing is required for the same starting
values for S, R, Q and Q
¯
. The revnor-based latch also requires
additional processing steps, but for differing starting values.
However, the number of combinations requiring additional
processing steps is the same.
In general, there are two combinations when setting the
latch which will require additional delay, and two combi-
nations when resetting the latch. This would have to be
factored in to any clocked design, such as a flip-flop, that
was to be built from these latches.
3.3.3. Overall comparison
The behaviour comparison suggests very little to choose from
amongst the three latches.
In terms of design, factors which impact area would include
the number of gates required and the number of garbage lines.
The revnor-based latch in Fig. 4(B) requires two gates and two
garbage lines, as does the Toffoli-based design in Fig. 3(A)
and the Fredkin-based design in Fig. 3(B).
As discussed above, each design has appropriate behaviour,
the only difference being the state achieved when the values
for S and R are both set to 1. This information may be of
use to a designer who has need of this type of behaviour
FIGURE 4. (A) A reversible latch based on the reversible NOR gate,
and (B) the same latch with fan-out removed.
TABLE 6. Behaviour of the Toffoli-based SR latch.
Initial values After gate processing New input values
SR 11 QQS
¯
þ
R
¯
þ
g
1
g
2
Q
þ
Q
þ
SR 11 QQ
¯
0 111100 111100 001111
1 111101 110101 001101
2 111110 111010 001110
3 111111 110011 001100
4 101100 101100 101111
5 101101 100101 101101
6 101110 101110 101111
7 101111 100111 101101
8 011100 011100 011111
9 011101 011101 011111
10 01 11 10 01 10 10 01 11 10
11 01 11 11 01 10 11 01 11 10
12 00 11 00 00 11 00 00 11 11
13 00 11 01 00 11 01 00 11 11
14 00 11 10 00 11 10 00 11 11
15 00 11 11 00 11 11 00 11 11
704 J. E. RICE
THE COMPUTER JOURNAL, Vol. 51 No. 6, 2008
