Analysis of the Universal Gates based on the Comparative Factors of Delay Propagation, Average Power Dissipation and Logical Effort

TLDR: In this paper, a comparative analysis of the universal logic gates has been carried out, based on the parameters of delay, Fan-out and power consumption, and the simulation results are in agreement to the literature presented regarding the logical effort of the gates.

Abstract: This paper illustrates the practical/working difference between the universal logic gates- NAND & NOR. The comparative analysis of the universal gates has been carried out, based on the parameters of delay, Fan-out and power consumption. The design and simulations are performed using Cadence Virtuoso tool in 45nm CMOS technology. The simulation results are in agreement to the literature presented regarding the logical effort of the gates. Here, the power dissipation and the delay calculations lead to conclusive results which are extensively discussed in this paper. The comparative assessment implemented for the gates is performed with same technology and same circuit designing techniques. Further, this work provides a decisive comment on- which amongst the two universal gates is more efficient for CMOS design.