Patent
Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling
Chao-Yuan Su,Pei-Haw Tsao,Hsin-Hui Lee,Chender Huang,Shang Y. Hou,Jeng Shin Pau,Tsai Hao Yi,Chenming Hu +7 more
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TLDR
In this paper, the first and second scribe lines intersect to define one corner point of a die and free area A1 is defined on the first scribe line and is defined by the equation A1=D1×S1.Abstract:
A multi-layered semiconductor structure with free areas limiting the placement of test keys. First and second scribe lines intersect to define one corner point of a die. The first and second scribe lines are part of the multilayered structure and at least one layer of the multi-layer structure is a low-k dielectric layer. Free area A1 is defined on the first scribe line and is defined by the equation A1=D1×S1, where D1 is the distance from the corner point of the die toward the main area of the die, and S1 is the width of the first scribe line. Free area AS is defined at the intersection of the first scribe line and the second scribe line adjacent the die and is defined by the equation AS=S1×S2, where S2 is the width of the second scribe line.read more
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Patent
Semiconductor processing system and methods using capacitively coupled plasma
Jang-Gyoo Yang,Matthew L. Miller,Xinglong Chen,Kien N. Chuc,Qiwei Liang,Shankar Venkataraman,Dmitry Lubomirsky +6 more
TL;DR: In this paper, a capacitively coupled plasma (CCP) unit is described inside a process chamber, and a pedestal is positioned below a gas reaction region into which the activated gas travels from the CCP unit.
Patent
Semiconductor processing systems having multiple plasma configurations
TL;DR: In this paper, the authors describe a system that includes a first plasma unit fluidly coupled with a first access of the chamber and configured to deliver a first precursor into the chamber through the first access.
Patent
Methods for etch of metal and metal-oxide films
TL;DR: In this paper, a method of selectively etching a metal-containing film from a substrate comprising a metal containing layer and a silicon oxide layer is proposed, which involves flowing a fluorine-containing gas into a plasma generation region of a substrate processing chamber, and applying energy to the fluorinecontaining gas to generate a plasma in the plasma generation area.
Patent
Method and apparatus for plasma dicing a semi-conductor wafer
Linnell Martinez,David Pays-Volard,Christopher D. Johnson,David W. Johnson,Russelll Westerman,Gordon M. Grivna +5 more
TL;DR: In this paper, a method for plasma dicing a substrate is presented, consisting of a process chamber having a wall, a plasma source adjacent to the wall of the process chamber, and a work piece support within the process chambers.
Patent
Methods for etch of sin films
TL;DR: In this paper, a method of selectively etching silicon nitride from a substrate comprising a silicon oxide layer and a silicon dioxide layer is proposed. But the method requires the substrate to be exposed to the reactive gas in the gas reaction region of the substrate processing chamber.
References
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Patent
Alignment method and apparatus therefor
TL;DR: In this paper, a method of aligning each of a plurality of processing areas arranged on a substrate with a predetermined transfer position in a static coordinate system XY for defining a moving position of said substrate, a pattern of a mask being transferred to each of the plurality of Processing areas, is described.
Proceedings ArticleDOI
MOSFET current drive optimization using silicon nitride capping layer for 65-nm technology node
Sergey Pidin,Toshihiko Mori,Ryou Nakamura,Takashi Saiki,R. Tanabe,S. Satoh,Masataka Kase,K. Hashimoto,Toshihiro Sugii +8 more
TL;DR: In this paper, the authors used extensive process simulations to analyze fabricated devices and developed optimization guidelines for NMOSFET strain engineering enabling further improvement of device current drivability with reducing the gate length.
Patent
Process for producing crackstops on semiconductor devices and devices containing the crackstops
TL;DR: In this paper, a process for making a crackstop on a semiconductor device is described, which involves creating and metallizing a groove surrounding the active region on a chip at the same time as other functional metallization is occurring, and selectively etching out the metal in the groove after final passivation.
Patent
Resin molded type semiconductor device having a conductor film
TL;DR: In this article, a guard ring is formed to cover the peripheral edge of the surface of a tetragonal semiconductor substrate, and slits or rows of small holes are formed in the corner portions of the guard ring.
Patent
Low capacitance interconnect structures in integrated circuits using a stack of low dielectric materials
Shin-Puu Jeng,Kelly J. Taylor +1 more
TL;DR: In this paper, an improved method and structure is provided for integrating HSQ and other low dielectric constant materials, which may have undesirable properties, into integrated circuit structures and processes, especially those requiring multiple levels of interconnect lines.