Proceedings ArticleDOI
ASIC design of MIPS based RISC processor for high performance
Agineti Ashok,V. Ravi +1 more
- pp 263-269
TLDR
The primary desire of this paper is to design and synthesize the MIPS processor by making utilization of register files and to insert the ALU forwarding unit in order to avoid the stalls and hardware interlocks.Abstract:
Objectives: The main aim of this paper is to implement 32Bit MIPS (Microprocessor Interlocked Pipeline Stages) RISC (Reduced Instruction Set Computer) Processor using Verilog HDL (hardware description language). Methods/Statistical analysis: The proposed algorithm analyzes the different stages of instruction decoding such as Instruction fetch module, Decoder module, Execution module and design theory based on 32Bit MIPS RISC Processor. In addition to that the algorithm uses pipelining concept which involves Instruction Fetch, Instruction Decode, Execution, Memory and Write Back modules of MIPS RISC processor based on 32Bit MIPS Instruction set in a single clock cycle. Findings: RISC is a processor which is intended to perform a tiny set of operations, to expand the rate (speed) of the processor. In general, the processor works with a huge number of instructions every second by bringing the information from the memory. In the event that the processor speed does not coordinate with memory access speed then hardware interlocks happen. In concurring with this there is one more issue called stalls because of instruction pipelining in the CPU design. The primary desire of this paper is to design and synthesize the MIPS processor by making utilization of register files and to insert the ALU forwarding unit in order to avoid the stalls and hardware interlocks. Application/Improvements: Based on the literature survey, the proposed method brings significant power efficiency improvements with enhanced performance and reduced power dissipation due to not only technology scaling but also a great deal of design efforts.read more
Citations
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Journal ArticleDOI
Universal Verification Methodology Based Verification of UART Protocol
Bidisha Kashyap,V. Ravi +1 more
Proceedings ArticleDOI
Design and Implementation of 32 bit MIPS based RISC Processor
TL;DR: In this article, a pipeline-based MIPS processor is presented and has different five processing stages instruction fetch (IF), instruction decode (ID), execution (EXE), memory (MEM), and write back(WB).
Book ChapterDOI
Variation-Tolerant In-Memory Digital Computations Using SRAM
TL;DR: In this article, a variation-tolerant in-memory digital computation SRAM with on-chip built-in self-test (BIST) module for testing some of the core Boolean functions before placing the chip in the functional mode.
Book ChapterDOI
Defect Detection and Defect-Tolerant Design of a Multi-port SRAM
TL;DR: In this paper, a register file with a structure of three-port SRAM cell and a differential current-mode sense amplifier for read circuitry is presented, and a read disturb fault for multi-port memories is tested on the faulty cell by simultaneous read operations with different numbers of ports.
Proceedings ArticleDOI
FPGA Implementation of a Novel Dual - BRAM Processor Architecture
TL;DR: This work proposes a novel high-speed processor architecture, developed around the traditional Harvard architecture with pipelining, having two block RAM (BRAM) modules implement the data memory, enabling to simultaneously read and write the instruction data and results respectively.
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